參數(shù)資料
型號(hào)： AD7890BNZ-4
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/28頁(yè)
文件大小： 0K
描述： IC DAS 12BIT 8CH 24-DIP
標(biāo)準(zhǔn)包裝： 15
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
分辨率（位）： 12 b
采樣率（每秒）： 117k
數(shù)據(jù)接口： 串行
電壓電源： 單電源
電源電壓： 5V
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 24-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 24-PDIP
包裝： 管件
AD7890
Rev. C | Page 18 of 28
Write Operation
Figure 11 shows a write operation to the control register of the
AD7890. The TFS input is taken low to indicate to the part that
a serial write is about to occur. TFS going low initiates the SCLK
output and this is used to clock data out of the processors serial
port and into the control register of the AD7890. The AD7890
control register requires only five bits of data. These are loaded
on the first five clock cycles of the serial clock with data on all
subsequent clock cycles being ignored. However, the part
requires six serial clock cycles to load data to the control
register. Serial data to be written to the AD7890 must be valid
on the falling edge of SCLK.
EXTERNAL CLOCKING MODE
The AD7890 is configured for its external clocking mode by
tying the SMODE pin of the device to a logic high. In this
mode, SCLK and RFS of the AD7890 are configured as inputs.
This external-clocking mode is designed for direct interface to
systems, which provide a serial clock output which is
synchronized to the serial data output including
microcontrollers such as the 80C51, 87C51, 68HC11, and
68HC05, and most digital signal processors.
Read Operation
Figure 12 shows the timing diagram for reading from the
AD7890 in the external clocking mode. RFS goes low to access
data from the AD7890. The serial clock input does not have to be
continuous. The serial data can be accessed in a number of bytes.
However, RFS must remain low for the duration of the data
transfer operation. Once again, 16th bits of data are transmitted
with one leading zero, followed by the three address bits in the
control register, followed by the 12-bit conversion result starting
with the MSB. If RFS goes low during the high time of SCLK,
the leading zero is clocked out from the falling edge of RFS (as
per Figure 12). If RFS goes low during the low time of SCLK,
the leading zero is clocked out on the next rising edge of SCLK.
This ensures that, regardless of whether RFS goes low during a
high time or low time of SCLK, the leading zero is valid on the
first falling edge of SCLK after RFS goes low, provided t14 and t17
are adhered to. Serial data is clocked out of the device on the
rising edge of SCLK and is valid on the falling edge of SCLK. At
the end of the read operation, the DATA OUT line is three-stated
by a rising edge on either the SCLK or RFS inputs, whichever
occurs first. If a serial read from the output register is in progress
when conversion is complete, the updating of the output register is
deferred until the serial data read is complete and RFS returns high.
Write Operation
Figure 13 shows a write operation to the control register of the
AD7890. As with self-clocking mode, the TFS input goes low to
indicate to the part that a serial write is about to occur. As before,
the AD7890 control register requires only five bits of data. These
are loaded on the first five clock cycles of the serial clock; data on all
subsequent clock cycles are ignored. However, the part requires six
serial clocks to load data to the control register. Serial data to be
written to the AD7890 must be valid on the falling edge of SCLK.
RFS (I)
SCLK (I)
DATA OUT (O)
NOTES:
1. (I) SIGNIFIES AN INPUT.
2. (O) SIGNIFIES AN OUTPUT.
THREE-STATE
LEADING
ZERO
DB10
DB0
DB11
A2
A1
A0
t14
t13
t15
t16
t17
t19
t19A
t18
01
35
7-
0
12
Figure 12. External Clocking (Slave) Mode Output Register Read
TFS (I)
SCLK (I)
DATA IN (I)
NOTES:
1. (I) SIGNIFIES AN INPUT.
2. (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.
A2
A1
A0
CONV
STBY
DON’T
CARE
DON’T
CARE
DON’T
CARE
t20
t22
t21
t23
01
35
7-
0
13
Figure 13. External Clocking (Slave) Mode Control Register Write
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