TIMING CHARACTERISTICS1, 2 Parameter A, B, Y Versions Unit Test Conditions/Comments <" />
參數(shù)資料
型號(hào)： AD7891YPZ-1
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/20頁(yè)
文件大小： 0K
描述： IC DAS 12BIT 8CH 44-PLCC
標(biāo)準(zhǔn)包裝： 1
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
分辨率（位）： 12 b
采樣率（每秒）： 500k
數(shù)據(jù)接口： 串行，并聯(lián)
電壓電源： 單電源
電源電壓： 5V
工作溫度： -55°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 管件
AD7891
–4–
REV. D
TIMING CHARACTERISTICS1, 2
Parameter
A, B, Y Versions
Unit
Test Conditions/Comments
tCONV
1.6
ms max
Conversion Time
Parallel Interface
t1
0
ns min
CS to RD/WR Setup Time
t2
35
ns min
Write Pulse Width
t3
25
ns min
Data Valid to Write Setup Time
t4
5
ns min
Data Valid to Write Hold Time
t5
0
ns min
CS to RD/WR Hold Time
t6
35
ns min
CONVST Pulse Width
t7
55
ns min
EOC Pulse Width
t8
35
ns min
Read Pulse Width
t9
3
25
ns min
Data Access Time after Falling Edge of
RD
t10
4
5
ns min
Bus Relinquish Time after Rising Edge of
RD
30
ns max
Serial Interface
t11
30
ns min
RFS Low to SCLK Falling Edge Setup Time
t12
3
20
ns max
RFS Low to Data Valid Delay
t13
25
ns min
SCLK High Pulse Width
t14
25
ns min
SCLK Low Pulse Width
t15
3
5
ns min
SCLK Rising Edge to Data Valid Hold Time
t16
3
15
ns max
SCLK Rising Edge to Data Valid Delay
t17
20
ns min
RFS to SCLK Falling Edge Hold Time
t18
4
0
ns min
Bus Relinquish Time after Rising Edge of
RFS
30
ns max
t18A
4
0
ns min
Bus Relinquish Time after Rising Edge of SCLK
30
ns max
t19
20
ns min
TFS Low to SCLK Falling Edge Setup Time
t20
15
ns min
Data Valid to SCLK Falling Edge Setup Time
t21
10
ns min
Data Valid to SCLK Falling Edge Hold Time
t22
30
ns min
TFS Low to SCLK Falling Edge Hold Time
NOTES
1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to
90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 2, 3, and 4.
3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
200 A
1.6V
TO
OUTPUT
PIN
50pF
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
相關(guān)PDF資料
PDF描述
LTC6906IS6#TRMPBF IC OSC SILICON 1MHZ TSOT23-6
AD7891YSZ-2 IC DAS 12BIT 8CH 44-MQFP
LTC6907IS6#TRPBF IC OSC SILICON 4MHZ TSOT23-6
LTC6906IS6#TRPBF IC OSC SILICON 1MHZ TSOT23-6
AD974AN IC DAS 16BIT 4CH 200KSPS 28-DIP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7891YPZ-1REEL 功能描述:IC DAS 12BIT 8CH 44-PLCC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤
AD7891YS1 制造商:AD 功能描述:New
AD7891YS-1 制造商:Analog Devices 功能描述:ADC Single 454.5ksps 12-bit Parallel/Serial 44-Pin MQFP
AD7891YS-1REEL 制造商:Analog Devices 功能描述:ADC Single 454.5ksps 12-bit Parallel/Serial 44-Pin MQFP T/R 制造商:Analog Devices 功能描述:ADC SGL 454.5KSPS 12-BIT PARALLEL/SERL 44MQFP - Tape and Reel
AD7891YS-2 制造商:Analog Devices 功能描述:ADC Single 500ksps 12-bit Parallel/Serial 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:8 CHANNEL, 12-BIT ADC I.C. - Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*