參數(shù)資料
型號： AD7892BNZ-2
廠商： Analog Devices Inc
文件頁數(shù)： 3/14頁
文件大?。?/td> 0K
描述： IC ADC 12BIT LP 500KSPS 24DIP
標準包裝： 15
位數(shù)： 12
采樣率（每秒）： 500k
數(shù)據(jù)接口： 串行，并聯(lián)
轉換器數(shù)目： 1
功率耗散（最大）： 90mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 24-DIP（0.300"，7.62mm）
供應商設備封裝： 24-PDIP
包裝： 管件
輸入數(shù)目和類型： 2 個單端，單極
AD7892
REV. C
–11–
The designed code transitions occur midway between successive
integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs). Output
coding is two’s complement binary with 1 LSB = FSR/4096 =
20 V/4096 = 4.88 mV for the
±10 V range and 1 LSB = FSR/
4096 = 10 V/4096 = 2.44 mV for the
±5 V range. The ideal
input/output transfer function for the AD7892-1 is shown in
Table I.
AD7892-2
The analog input section for the AD7892-2 contains no biasing
resistors. The analog input looks directly into the track/hold
input stage. The analog input range on the VIN1 input is 0 V to
+2.5 V. The VIN2 input can be left unconnected but if it is
connected to a potential then that potential must be AGND.
The VIN1 input connects directly to the input sampling capacitor
of the AD7892-2’s track/hold. The value of this input sampling
capacitor is nominally 10 pF.
Once again, the designed code transitions occur midway be-
tween successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,
5/2 LSBs). Output coding is straight (natural) binary with
1 LSB = FSR/4096 = 2.5 V/4096 = 0.61 mV. The ideal input/
output transfer function for the AD7892-2 is shown in Table II.
Table I. Ideal Input/Output Code Table for the AD7892-1
Digital Output
Analog Input
Code Transition
+FSR/2 – 3/2 LSB1, 2 (9.99268 or 4.99634)3
011 . . . 110 to 011 . . . 111
+FSR/2 – 5/2 LSBs (9.98779 or 4.99390)
011 . . . 101 to 011 . . . 110
+FSR/2 – 7/2 LSBs (9.98291 or 4.99146)
011 . . . 100 to 011 . . . 101
AGND + 3/2 LSB (0.00732 or 0.00366)
000 . . . 001 to 000 . . . 010
AGND + 1/2 LSB (0.00244 or 0.00122)
000 . . . 000 to 000 . . . 001
AGND – 1/2 LSB (–0.00244 or –0.00122)
111 . . . 111 to 000 . . . 000
AGND – 3/2 LSB (–0.00732 or –0.00366)
111 . . . 110 to 111 . . . 111
–FSR/2 + 5/2 LSB (–9.98779 or – 4.99390)
100 . . . 010 to 100 . . . 011
–FSR/2 + 3/2 LSB (–9.99268 or – 4.99634)
100 . . . 001 to 100 . . . 010
–FSR/2 + 1/2 LSB (–9.99756 or – 4.99878)
100 . . . 000 to 100 . . . 001
NOTES
1FSR is full-scale range and REF IN = +2.5 V, is 20 V for the
±10 V range and 10 V
for the
±5 V range.
21 LSB = FSR/4096 = 4.88 mV (
±10 V range) and 2.44 mV (±5 V range) with REF
IN = +2.5 V.
3
± 10 V range or ±5 V range.
Table II. Ideal Input/Output Code Table for the AD7892-2
Digital Output
Analog Input
Code Transition
+FSR – 3/2 LSB
1, 2 (2.499084 V)
111 . . . 110 to 111 . . . 111
+FSR – 5/2 LSBs (2.498474 V)
111 . . . 110 to 111 . . . 110
+FSR – 7/2 LSBs (2.497864 V)
111 . . . 100 to 111 . . . 101
AGND + 5/2 LSB (0.001526 V)
000 . . . 010 to 010 . . . 011
AGND + 3/2 LSB (0.00916 V)
000 . . . 001 to 001 . . . 010
AGND + 1/2 LSB (0.000305 V)
000 . . . 000 to 000 . . . 001
NOTES
1FSR is full-scale range and is 2.5 V with REF IN = +2.5 V.
21 LSB = FSR/4096 = 0.61 mV with REF IN = +2.5 V.
AD7892-3
Figure 5 shows the analog input section for the AD7892-3. The
analog input range is
±2.5 V on the VIN1 input. The VIN2 input
can be left unconnected but if it is connected to a potential then
that potential must be AGND. The input resistance on the VIN1
is 1.8 k
nominal. As a result, the VIN1 input should be driven
from a low impedance source. The resistor attenuator stage is
followed by the high input impedance stage of the track/hold
amplifier. This resistor attenuator stage allows the input voltage
to go to
±7 V without damaging the AD7892-3.
The designed code transitions occur midway between succes-
sive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs).
Output coding is two’s complement binary with 1 LSB = FSR/
4096 = 5 V/4096 = 1.22 mV with REF IN = +2.5 V. The ideal
input/output transfer function for the AD7892-3 is shown in
Table III.
+2.5
REFERENCE
REF OUT/
REF IN
VIN1
VIN2*
AGND
TO HIGH
IMPEDANCE
SHA INPUT
TO ADC
REFERENCE
CIRCUITRY
2k
3.25k
* UNCONNECTED INTERNALLY ON THE AD7892-3
Figure 5. AD7892-3 Analog Input Structure
Table III. Ideal Input/Output Code Table for the AD7892-3
Digital Output
Analog Input
Code Transition
+FSR/2 – 3/2 LSB
1, 2 (2.49817)
011 . . . 110 to 011 . . . 111
+FSR/2 – 5/2 LSBs (2.49695)
011 . . . 110 to 011 . . . 110
+FSR/2 – 7/2 LSBs (2.49573)
011 . . . 110 to 011 . . . 101
AGND + 3/2 LSB (0.00183)
000 . . . 001 to 000 . . . 010
AGND + 1/2 LSB (0.00061)
000 . . . 000 to 000 . . . 001
AGND – 1/2 LSB (–0.00061)
111 . . . 111 to 000 . . . 000
AGND – 3/2 LSB (–0.00183)
111 . . . 110 to 111 . . . 111
–FSR/2 + 5/2 LSB (–2.49695)
100 . . . 010 to 100 . . . 011
–FSR/2 + 3/2 LSB (–2.49817)
100 . . . 001 to 100 . . . 010
–FSR/2 + 1/2 LSB (–2.49939)
100 . . . 000 to 100 . . . 001
NOTES
1FSR is full-scale range and is 5 V with REF IN = +2.5 V.
21 LSB = FSR/4096 = 1.22 mV with REF IN = +2.5 V.
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