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參數(shù)資料
| 型號(hào)： | AD7892BRZ-1REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/14頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT LP 500KSPS 24SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 90mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極 |
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AD7892
–4–
REV. C
TIMING CHARACTERISTICS1, 2
A, B
S
Parameter
Versions
Version
Unit
Test Conditions/Comments
tCONV
1.47
s max
Conversion Time for AD7892-3
1.6
1.68
s max
Conversion Time for AD7892-1, AD7892-2
tACQ
200
ns min
Acquisition Time for AD7892-3
400
320
ns min
Acquisition Time for AD7892-1, AD7892-2
Parallel Interface
t1
35
45
ns min
CONVST Pulsewidth
t2
60
ns min
EOC Pulsewidth
t3
0
ns min
EOC Falling Edge to CS Falling Edge Setup Time
t4
0
ns min
CS to RD Setup Time
t5
35
45
ns min
Read Pulsewidth
t6
3
35
40
ns max
Data Access Time After Falling Edge of
RD
t7
4
5
ns min
Bus Relinquish Time After Rising Edge of
RD
30
40
ns max
t8
0
ns min
CS to RD Hold Time
t9
200
ns min
RD to CONVST Setup Time
Serial Interface
t10
30
35
ns min
RFS Low to SCLK Falling Edge Setup Time
t11
3
25
30
ns max
RFS Low to Data Valid Delay
t12
25
ns min
SCLK High Pulsewidth
t13
25
ns min
SCLK Low Pulsewidth
t14
3
5
ns min
SCLK Rising Edge to Data Valid Hold Time
t15
3
25
30
ns max
SCLK Rising Edge to Data Valid Delay
t16
20
30
ns min
RFS to SCLK Falling Edge Hold Time
t17
4
0
ns min
Bus Relinquish Time after Rising Edge of
RFS
30
ns max
t17A
4
0
ns min
Bus Relinquish Time after Rising Edge of SCLK
30
ns max
NOTES
1Sample tested at +25
°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2See Figures 2 and 3.
3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
5Assumes CMOS loads on the data bits. With TTL loads, more current is drawn from the data lines and the
RD to CONVST time needs to be extended to 400 ns min.
Specifications subject to change without notice.
1.6mA
+1.6V
200 A
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7892 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
(VDD = +5 V
5%, AGND = DGND = 0 V, REF IN = +2.5 V)
WARNING!
ESD SENSITIVE DEVICE
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