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參數(shù)資料
| 型號： | AD7894BR-10 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | SWITCH SLIDE SPDT R/A .5A PCB |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 131K |
| 代理商： | AD7894BR-10 |
–3–
REV. 0
AD7894
Parameter
A Versions
l
B Versions
1
Units
Test Conditions/Comments
POWER REQUIREMENTS
V
DD
I
DD
Power Dissipation
Power-Down Mode
I
DD
@ T
MIN
to T
MAX
Power Dissipation T
MIN
to T
MAX
+5
5.5
27.5
+5
5.5
27.5
V nom
mA max
mW max
±
5% for Specified Performance
Digital Inputs @ V
DD
, V
DD
= 5 V
±
5%
Typically 20 mW
20
100
20
100
μ
A max
μ
W max
Digital Inputs @ GND, V
DD
= 5 V
±
5%
Typ 15
μ
W
NOTES
1
Temperature ranges are as follows: A, B Versions: –40
°
C to +85
°
C.
2
Applies to Mode 1 operation. See Operating Modes section.
3
See Terminology.
4
Sample tested @ +25
°
C to ensure compliance.
5
This 10
μ
s includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of
CONVST
, whereas conversion is timed from the falling
edge of
CONVST
, for narrow
CONVST
pulsewidth the conversion time is effectively the “wake-up” time plus conversion time, hence 10
μ
s. This can be seen from
Figure 3. Note that if the
CONVST
pulsewidth is greater than 5
μ
s, the effective conversion time will increase beyond 10
μ
s.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2
Parameter
A, B Versions
Units
Test Conditions/Comments
t
1
t
2
t
3
t
4
40
31.25
2
31.25
2
60
3
ns min
ns min
ns min
ns max
CONVST
Pulsewidth
SCLK High Pulsewidth
SCLK Low Pulsewidth
Data Access Time after Falling Edge of SCLK
V
DD
= 5 V
±
5%
Data Hold Time after Falling Edge of SCLK
Bus Relinquish Time after Falling Edge of SCLK
t
5
t
6
10
20
4
ns min
ns max
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2
The SCLK maximum frequency is 16 MHz. Care must be taken when interfacing to account for the data access time, t
4
, and the setup time required for the user’s
processor. These two times will determine the maximum SCLK frequency with which the user’s system can operate. See Serial Interface section for more information.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
6
, quoted in the timing characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(V
DD
= +5 V
6
5%, GND = 0 V, REF IN = +2.5 V)
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25
°
C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7 V
Analog Input Voltage to GND
AD7894-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
17 V
AD7894-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
7 V
AD7894-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +10 V
Reference Input Voltage to GND . . . . –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to GND . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40
°
C to +85
°
C
Storage Temperature Range . . . . . . . . . . . –65
°
C to +150
°
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150
°
C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 170
°
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220
°
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7894 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD7894BR-10REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 14-bit Serial 8-Pin SOIC N T/R |
| AD7894BR-10REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 14-bit Serial 8-Pin SOIC N T/R |
| AD7894BR-3 | 功能描述:IC ADC 14BIT SRL T/H LP 8-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7894BR-3REEL | 功能描述:IC ADC 14BIT SRL T/H LP 8-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7894BR-3REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 14-bit Serial 8-Pin SOIC N T/R |
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