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參數(shù)資料
| 型號： | AD7894BRZ-10REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SRL T/H LP 8SOIC |
| 標準包裝： | 2,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 27.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，雙極 |
AD7894
–4–
REV. 0
ORDERING GUIDE
Temperature
Package
Model
Range
INL
Input Range
SNR
Description
Option
AD7894AR-10
–40
°C to +85°C
±2 LSB
±10 V
77 dB
8-Lead Narrow Body SOIC
SO-8
AD7894BR-10
–40
°C to +85°C
±1.5 LSB
±10 V
77 dB
8-Lead Narrow Body SOIC
SO-8
AD7894AR-3
–40
°C to +85°C
±2 LSB
±2.5 V
77 dB
8-Lead Narrow Body SOIC
SO-8
AD7894BR-3
–40
°C to +85°C
±1.5 LSB
±2.5 V
77 dB
8-Lead Narrow Body SOIC
SO-8
AD7894AR-2
–40
°C to +85°C
±2 LSB
0 V to +2.5 V
77 dB
8-Lead Narrow Body SOIC
SO-8
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Description
1
REF IN
Voltage Reference Input. An external reference source should be connected to this pin to provide the
reference voltage for the AD7894’s conversion process. The REF IN input is buffered on-chip. The
nominal reference voltage for correct operation of the AD7894 is +2.5 V.
2VIN
Analog Input Channel. The analog input range is
±10 V (AD7894-10), ±2.5 V (AD7894-3) and 0 V to
+2.5 V (AD7894-2).
3
GND
Analog Ground. Ground reference for track/hold, comparator, digital circuitry and DAC.
4
SCLK
Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7894.
A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for
10 ns after this falling edge so data can be accepted on the falling edge when a fast serial clock is used.
The serial clock input should be taken low at the end of the serial data transmission.
5
SDATA
Serial Data Output. Serial data from the AD7894 is provided at this output. The serial data is clocked
out by the falling edge of SCLK, but the data can also be read on the falling edge of SCLK. This is pos-
sible because data bit N is valid for a specified time after the falling edge of SCLK (data hold time) (see
Figure 5). Sixteen bits of serial data are provided as two leading zeroes followed by the 14 bits of conver-
sion data. On the 16th falling edge of SCLK, the SDATA line is held for the data hold time and then
disabled (three-stated). Output data coding is twos complement for the AD7894-10 and AD7894-3, and
straight binary for the AD7894-2.
6
BUSY
The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin will go high on
the falling edge of
CONVST and will return low when the conversion is complete.
7
CONVST
Conversion Start. Edge-triggered logic input. On the falling edge of this input, the track/hold goes into its
hold mode and conversion is initiated. If
CONVST is low at the end of conversion, the part goes into
power-down mode. In this case, the rising edge of
CONVST will cause the part to begin waking up.
8VDD
Positive supply voltage, +5 V
± 5%.
1.6mA
400 A
+1.6V
TO
OUTPUT
PIN
50pF
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
PIN CONFIGURATION
SOIC (SO-8)
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
REF IN
VIN
GND
VDD
CONVST
BUSY
SDATA
SCLK
AD7894
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