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參數(shù)資料
| 型號(hào)： | AD7894BRZ-3 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SRL T/H LP 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 27.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，雙極 |
AD7894
–11–
REV. 0
Dynamic Performance (Mode 1 Only)
With a conversion time of 5
s, the AD7894 is ideal for wide
bandwidth signal processing applications. These applications
require information on the ADC’s effect on the spectral con-
tent of the input signal. Signal to (Noise + Distortion), Total
Harmonic Distortion, Peak Harmonic or Spurious Noise and
Intermodulation Distortion are all specified. Figure 11 shows a
typical FFT plot of a 10 kHz,
±10 V input after being digitized
by the AD7894-10 operating at a 160 kHz sampling rate. The
signal to (noise + distortion) ratio is 80.24 dB and the total
harmonic distortion is –96.35 dB.
The formula for signal to (noise + distortion) ratio (see Ter-
minology section) is related to the resolution or number of bits
in the converter. Rewriting the formula, below, gives a mea-
sure of performance expressed in effective number of bits (N):
N
=
(SNR –1.76)
6.02
where SNR is Signal to (Noise + Distortion) Ratio.
FREQUENCY – kHz
0
–140
080
10
dBs
20
30
40
50
60
70
–20
–60
–80
–100
–120
–40
fS = 160kHz
FIN = 10kHz
SNR = 80.24dB
THD = –96.35dB
Figure 11. AD7894 FFT Plot
The effective number of bits for a device can be calculated from
its measured signal to (noise + distortion) ratio. Figure 12
shows a typical plot of effective number of bits versus frequency
for the AD7894 from dc to fSAMPLING/2. The sampling fre-
quency is 160 kHz. The plot shows that the AD7894 converts
an input sine wave of 10 kHz to an effective numbers of bits of
13.00, which equates to a signal to (noise + distortion) level of
80.02 dB.
FREQUENCY – kHz
14
13
9
10
1000
100
ENOBs
12
11
10
Figure 12. Effective Number of Bits vs. Frequency
Power Considerations
In the automatic power-down mode the part may be operated at
a sample rate that is considerably less than 160 kHz. In this
case, the power consumption will be reduced and will depend
on the sample rate. Figure 13 shows a graph of the power con-
sumption versus sampling rates from 1 Hz to 100 kHz in the
automatic power-down mode. The conditions are 5 V supply
+25
°C. The SCLK pin was held low and no data was read from
the part.
SAMPLING FREQUENCY – Hz
100
0.1
1
100000
10
POWER
–
mW
100
1000
10000
10
1
Figure 13. Power vs. Sampling Rate in Automatic Power-
Down Mode
82
81
78
–40
80
–20
0
20
40
60
80
79
fS = 160kHz
FIN = 10kHz
TEMPERATURE – C
SNR+D
–
dB
Figure 14. SNR + D vs. Temperature
FREQUENCY – kHz
100
80
10
1000
100
THD
–
dB
90
70
60
50
40
30
20
10
0
Figure 15. THD vs. Frequency
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