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參數(shù)資料
| 型號： | AD7898AR-10 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 5 V, 12-Bit, Serial 220 kSPS ADC in an 8-Lead Package |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 184K |
| 代理商： | AD7898AR-10 |
–11–
REV. 0
AD7898
CONVST
SCLK
SERIAL READ
OPERATION
CONVERSION
ENDS
3.3 s LATER
OUTPUT
SERIAL
SHIFT
REGISTER
IS RESET
CONVERSION IS
INITIATED AND
TRACK/HOLD GOES INTO
HOLD
READ OPERATION
SHOULD END
100ns
PRIOR TO NEXT
FALLING EDGE OF
CONVST
1
16
t
1
t
CONVERT
= 3.3 s
100ns MIN
Figure 6. Serial Interface Timing Diagram Mode 0
ZERO
FOUR LEADING ZEROS
DB11
DB10
DB2
DB0
Z
DB1
ZERO
ZERO
SDATA
THREE-STATE
THREE-STATE
SCLK
1
5
15
2
3
4
16
14
t
2
t
3
t
5
t
4
t
6
Figure 7. Data Read Operation in Mode 0
Figure 7 shows the timing diagram for the read operation to the
AD7898 in Mode 0. The serial clock input (SCLK) provides
the clock source for the serial interface. Serial data is clocked
out from the SDATA line on the falling edge of this clock and is
valid on both the rising and falling edges of SCLK, depending
on the SCLK frequency used. The advantage of having the data
valid on both the rising and falling edges of the SCLK is that it
gives the user greater flexibility in interfacing to the part and
allows a wider range of microprocessor and microcontroller
interfaces to be accommodated. This also explains the two tim-
ing figures, t
4
and t
5,
that are quoted on the diagram.
The time, t
4
, specifies how long after the falling edge of the
SCLK the next data bit becomes valid, whereas the time, t
5
,
specifies for how long after the falling edge of the SCLK the
current data bit is valid. The first leading zero is clocked out on
the first rising edge of SCLK. Note that the first leading zero
will be valid on the first falling edge of SCLK even though the
data access time is specified at t
4
for the other bits (see Timing
Specifications). The reason the first bit will be clocked out faster
than the other bits is due to the internal architecture of the part.
Sixteen clock pulses must be provided to the part to access to
full conversion result. The AD7898 provides four leading zeros,
followed by the 12-bit conversion result starting with the MSB
(DB11). The last data bit to be clocked out on the fifteenth
falling clock edge is the LSB (DB0). On the 16th falling edge of
SCLK, the LSB (DB0) will be valid for a specified time to allow
the bit to be read on the falling edge of the SCLK, then the
SDATA line is disabled (three-stated). After this last bit has
been clocked out, the SCLK input should return low and remain
low until the next serial data read operation. If there are extra
clock pulses after the 16th clock, the AD7898 will start over,
outputting data from its output register, and the data bus will no
longer be three-stated even when the clock stops. Provided the
serial clock has stopped before the next falling edge of
CONVST
,
the AD7898 will continue to operate correctly with the output
shift register being reset on the falling edge of
CONVST
. How-
ever, the SCLK line must be low when
CONVST
goes low in
order to correctly reset the output shift register.
The 16 serial clock input does not have to be continuous during
the serial read operation. The 16 bits of data (four leading zeros
and 12-bit conversion result) can be read from the AD7898 in a
number of bytes.
The AD7898 counts the serial clock edges to know which bit
from the output register should be placed on the SDATA out-
put. To ensure that the part does not lose synchronization, the
serial clock counter is reset on the falling edge of the
CONVST
input, provided the SCLK line is low. The user should ensure
that the SCLK line remains low until the end of the conversion.
When the conversion is complete, the output register will be
loaded with the new conversion result and can be read from the
ADC with 16 clock cycles of SCLK.
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相關代理商/技術參數(shù) |
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|---|---|
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