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參數(shù)資料
| 型號： | AD7898AR-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 5 V, 12-Bit, Serial 220 kSPS ADC in an 8-Lead Package |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 184K |
| 代理商： | AD7898AR-3 |
–5–
REV. 0
AD7898
PIN FUNCTION DESCRIPTIONS
Pin
No.
Pin
Mnemonic
Function
1
REF IN
Voltage Reference Input. An external reference source should be connected to this pin to provide the
reference voltage for the AD7898’s conversion process. The REF IN input is buffered on-chip. The
nominal reference voltage for correct operation of the AD7898 is 2.5 V
±
5%. A 0.1
μ
F capacitor
should be placed on the REF IN pin.
Analog Input Channel. The analog input range is
±
10 V (AD7898-10) and
±
2.5 V (AD7898-3).
Analog Ground. Ground reference for track/hold, comparator, digital circuitry, and DAC.
Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7898.
When in Mode 0 operation, a new serial data bit is clocked out on the falling edge of this serial clock.
In Mode 0, data is guaranteed valid for 20 ns after this falling edge so that data can be accepted on the
falling edge when a fast serial clock is used. The serial clock input should be taken low at the end of
the serial data transmission. When in Mode 1 operation, SCLK also provides the serial clock for
accessing data from the part as in Mode 0, but this clock input is also used as the clock source for the
AD7898’s conversion process when in Mode 1.
Serial Data Output. Serial data from the AD7898 is provided at this output. The serial data is clocked
out by the falling edge of SCLK, but the data can also be read on the falling edge of SCLK. This is
possible because data bit N is valid for a specified time after the falling edge of SCLK (data hold time).
Sixteen bits of serial data are provided with four leading zeros followed by the 12 bits of conversion data,
which is provided MSB first. On the 16th falling edge of SCLK, the SDATA line is held for the data
hold time and then is disabled (three-stated). Output data coding is two’s complement for the AD7898.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial inter-
face of the AD7898 will operate.
Chip Select/Convert Start. This pin is
CONVST
, an edge-triggered logic input when in Mode 0 operation.
On the falling edge of this input, the track/hold goes into its hold mode, and conversion is initiated.
When in Mode 1 operation, this pin is Chip Select, an active low logic input. This input provides the
dual function of initiating conversions on the AD7898 and also frames the serial data transfer.
Power Supply Input, 5 V
±
5%.
2
3
4
V
IN
GND
SCLK
5
SDATA
6
V
DRIVE
7
CS
/
CONVST
8
V
DD
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