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參數(shù)資料
| 型號(hào)： | AD7899SR-1 |
| 英文描述： | 12-Bit Rail-to-Rail Micropower DAC with Clear Input; Package: SO; No of Pins: 8; Temperature Range: 0°C to +70°C |
| 中文描述： | 模擬到數(shù)字轉(zhuǎn)換器，14位 |
| 文件頁(yè)數(shù)： | 4/20頁(yè) |
| 文件大?。?/td> | 191K |
| 代理商： | AD7899SR-1 |
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REV. B
AD7890
–4–
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
(A, B, S Versions)
Parameter
Unit
Conditions/Comments
f
CLKIN3
100
2.5
0.3
×
t
CLK IN
0 3
×
t
CLK IN
25
25
5.9
100
kHz min
MHz max
ns min
ns min
ns max
ns max
μ
s max
ns min
Master Clock Frequency. For Specified Performance
t
CLK IN LO
t
CLK IN HI
tr
4
tf
4
t
CONVERT
t
CST
Self-Clocking Mode
t
1
t
25
t
3
t
4
t
55
t
6
t
76
t
8
Master Clock Input Low Time
Master Clock Input High Time
Digital Output Rise Time. Typically 10 ns
Digital Output Fall Time. Typically 10 ns
Conversion Time
CONVST
Pulsewidth
t
CLK IN HI
+ 50
25
t
CLK IN HI
t
CLK IN LO
20
40
50
0
t
CLK IN
+ 50
0
20
10
20
ns max
ns max
ns nom
ns nom
ns max
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
RFS
Low to SCLK Falling Edge
RFS
Low to Data Valid Delay
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Rising Edge to Data Valid Delay
SCLK Rising Edge to
RFS
Delay
Bus Relinquish Time after Rising Edge of SCLK
TFS
Low to SCLK Falling Edge
t
9
t
10
t
11
t
12
Data Valid to
TFS
Falling Edge Setup Time (A2 Address Bit)
Data Valid to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Hold Time
TFS
to SCLK Falling Edge Hold Time
External-Clocking Mode
t
13
t
145
t
15
t
16
t
175
t
18
t
196
t
19A6
t
20
t
21
t
22
t
23
20
40
50
50
35
20
50
90
20
10
15
40
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
RFS
Low to SCLK Falling Edge Setup Time
RFS
Low to Data Valid Delay
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Rising Edge to Data Valid Delay
RFS
to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of
RFS
Bus Relinquish Time after Rising Edge of SCLK
TFS
Low to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Hold Time
TFS
to SCLK Falling Edge Hold Time
NOTES
1
Sample tested at –25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 8 to 11.
3
The AD7890 is production tested with f
CLK IN
at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz.
4
Specified using 10% and 90% points on waveform of interest.
5
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
TO OUTPUT
PIN
+2.1V
1.6mA
200 A
50pF
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
(V
DD
= 5 V 5%, AGND = DGND = 0 V, REF IN = 2.5 V, f
CLK IN
= 2.5 MHz external, MUX OUT
connected to SHA IN.)
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