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參數(shù)資料
| 型號： | AD7904BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP |
| 中文描述： | 4-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 411K |
| 代理商： | AD7904BRU |
–10–
AD7904/AD7914/AD7924
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock
input is also used as the clock source for the AD7904/AD7914/AD7924’s conversion process.
Data In. Logic Input. Data to be written to the AD7904/AD7914/AD7924’s Control Register is
provided on this input and is clocked into the register on the falling edge of SCLK (see Control Register section).
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7904/AD7914/AD7924 and also frames the serial data transfer.
Analog Ground. Ground reference point for all analog circuitry on the AD7904/AD7914/AD7924. All
analog input signals and any external reference signal should be referred to this AGND voltage. All
AGND pins should be connected together.
Analog Power Supply Input. The AV
DD
range for the AD7904/AD7914/AD7924 is from 2.7 V to 5.25 V.
For the 0 V to 2
×
REF
IN
range, AV
DD
should be from 4.75 V to 5.25 V.
Reference Input for the AD7904/AD7914/AD7924. An external reference must be applied to this
input. The voltage range for the external reference is 2.5 V
±
1% for specified performance.
Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed
into the on-chip track/hold. The analog input channel to be converted is selected by using the address
bits ADD1 and ADD0 of the control register. The address bits, in conjunction with the SEQ1 and
SEQ0 bits, allow the Sequencer to be programmed. The input range for all input channels can extend
from 0 V to REF
IN
or 0 V to 2
×
REF
IN
as selected via the RANGE bit in the control register. Any
unused input channels should be connected to AGND to avoid noise pickup.
Data Out. Logic Output. The conversion result from the AD7904/AD7914/AD7924 is provided on
this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input.
The data stream from the AD7904 consists of two leading zeros, two address bits indicating which channel
the conversion result corresponds to, followed by the eight bits of conversion data, followed by four
trailing zeros, provided MSB first; the data stream from the AD7914 consists of two leading zeros, two
address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of
conversion data, followed by two trailing zeros, also provided MSB first; the data stream from the AD7924
consists of two leading zeros, two address bits indicating which channel the conversion result corresponds
to, followed by the 12 bits of conversion data provided MSB first. The output coding may be selected
as straight binary or twos complement via the CODING bit in the control register.
Logic Power Supply Input. The voltage supplied at this pin determines what voltage the serial interface of
the AD7904/AD7914/AD7924 will operate at.
2
DIN
3
CS
4, 8, 13, 16
AGND
5, 6
AV
DD
7
REF
IN
12–9
V
IN
0–V
IN
3
14
DOUT
15
V
DRIVE
PIN CONFIGURATION
16-Lead TSSOP
1
AD7904/
AD7914/
AD7924
SCLK
AGND
16
TOP VIEW
(Not to Scale)
2
DIN
V
DRIVE
DOUT
15
3
CS
14
4
AGND
AGND
13
5
AV
DD
AV
DD
REF
IN
AGND
V
IN
0
V
IN
1
V
IN
2
V
IN
3
12
6
11
7
10
8
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7914 | 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP |
| AD7914BRU | 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP |
| AD7924 | 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP |
| AD7924BRU | 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP |
| AD7908 | 8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP |
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