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參數資料
| 型號： | AD7904WYRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 15/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 4CH W/SEQ 16TSSOP |
| 標準包裝： | 1 |
| 位數： | 8 |
| 采樣率（每秒）： | 1M |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 13.5mW |
| 電壓電源： | 單電源 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 標準包裝 |
| 輸入數目和類型： | 4 個單端，單極 |
| 其它名稱： | AD7904WYRUZ-REEL7DKR |
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AD7904/AD7914/AD7924
Data Sheet
Rev. C | Page 22 of 32
MODES OF OPERATION
The AD7904/AD7914/AD7924 have three modes of operation.
These modes are designed to provide flexible power management
options. These options can be chosen to optimize the power
dissipation/throughput rate ratio for differing application require-
ments. The mode of operation of the AD7904/AD7914/AD7924
is controlled by the power management bits, PM1 and PM0, in
the control register (see Table 9). When power supplies are first
applied to the AD7904/AD7914/AD7924, care should be taken to
ensure that the part is placed in the required mode of operation
(see the Powering Up the AD7904/AD7914/AD7924 section).
NORMAL MODE (PM1 = PM0 = 1)
Normal mode is intended for the fastest throughput rate perfor-
mance. Because the AD7904/AD7914/AD7924 remain fully
powered up at all times, the user does not need to worry about
power-up times. Figure 20 shows the general diagram of the
operation of the AD7904/AD7914/AD7924 in this mode.
NOTES
1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES.
1
12
CS
SCLK
DOUT
DIN
16
DATA IN TO CONTROL REGISTER
2 LEADING ZEROS + 2 CHANNEL IDENTIFIER BITS
+ CONVERSION RESULT
03087-
020
Figure 20. Normal Mode Operation
The conversion is initiated on the falling edge of CS; the track-
and-hold enters hold mode as described in the Serial Interface
section. The data presented to the AD7904/AD7914/AD7924
on the DIN line during the first 12 clock cycles of the data
transfer is loaded into the control register (provided that the
WRITE bit is set to 1). In normal mode, the part remains fully
powered up at the end of the conversion as long as the PM1 and
PM0 bits are set to 1 in the write transfer during that same
conversion. To ensure continued operation in normal mode,
PM1 and PM0 must both be set to 1 on every data transfer,
assuming that a write operation is taking place. If the WRITE
bit is set to 0, the power management bits are left unchanged,
and the part remains in normal mode.
Sixteen serial clock cycles are required to complete the conversion
and to access the conversion result. The track-and-hold returns
to track mode on the 14th SCLK falling edge. CS may then idle
high until the next conversion or it may idle low until some
time prior to the next conversion (effectively idling CS low).
When a data transfer is complete (DOUT has returned to three-
state), another conversion can be initiated after the quiet time,
tQUIET, has elapsed by bringing CS low again.
FULL SHUTDOWN MODE (PM1 = 1, PM0 = 0)
In full shutdown mode, all internal circuitry on the AD7904/
AD7914/AD7924 is powered down. The part retains information
in the control register during full shutdown. The AD7904/AD7914/
AD7924 remain in full shutdown until the power management
bits in the control register, PM1 and PM0, are changed.
If a write to the control register occurs while the part is in full
shutdown, and the power management bits are changed to
PM0 = PM1 = 1 (that is, normal mode), the part will begin to
power up on the CS rising edge. The track-and-hold, which was
in hold mode while the part was in full shutdown, returns to
track mode on the 14th SCLK falling edge.
To ensure that the part is fully powered up, tPOWER-UP (t12) should
have elapsed before the next CS falling edge. Figure 21 shows
the general diagram for this sequence.
AUTO SHUTDOWN MODE (PM1 = 0, PM0 = 1)
In auto shutdown mode, the AD7904/AD7914/AD7924 auto-
matically enter shutdown at the end of each conversion when
the control register is updated. When the part is in auto shutdown,
the track-and-hold is in hold mode. Figure 22 shows the general
diagram of the operation of the AD7904/AD7914/AD7924 in
this mode.
In auto shutdown mode, all internal circuitry on the AD7904/
AD7914/AD7924 is powered down. The part retains information
in the control register during auto shutdown. The AD7904/
AD7914/AD7924 remain in shutdown until the next CS falling
edge that it receives. On this CS falling edge, the track-and-hold,
which was in hold mode while the part was in shutdown, returns
to track mode. Wake-up time from auto shutdown is 1 s max-
imum, and the user should ensure that 1 s has elapsed before
attempting a valid conversion.
When running the AD7904/AD7914/AD7924 with a 20 MHz
clock, one 16 SCLK dummy cycle should be sufficient to ensure
that the part is fully powered up. During this dummy cycle, the
contents of the control register should remain unchanged;
therefore, the WRITE bit should be set to 0 on the DIN line.
This dummy cycle effectively halves the throughput rate of the
part, with every other conversion result being valid. In auto
shutdown mode, the power consumption of the part is greatly
reduced because the part enters shutdown at the end of each
conversion. When the control register is programmed to move
into auto shutdown mode, it does so at the end of the con-
version. The user can move the ADC in and out of the low
power state by controlling the CS signal.
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