參數(shù)資料
型號(hào)： AD7908
廠商： Analog Devices, Inc.
英文描述： 8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP
中文描述： 8通道，1 MSPS的，8-/10-/12-Bit與序列ADC的20引腳TSSOP封裝
文件頁(yè)數(shù)： 21/24頁(yè)
文件大?。?/td> 607K
代理商： AD7908
AD7908/AD7918/AD7928
REV. A
THROUGHPUT (kSPS)
10
0
100
200
300
P
1
0.1
0.01
50
150
250
350
AV
DD
= 5V
AV
DD
= 3V
Figure 16. AD7928 Power vs. Throughput Rate
SERIAL INTERFACE
Figures 17, 18, and 19 show the detailed timing diagrams
for serial interfacing to the AD7908, AD7918, and AD7928,
respectively. The serial clock provides the conversion clock and
also controls the transfer of information to and from the
AD7908/AD7918/AD7928 during each conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track-and-hold into hold mode,
takes the bus out of three-state; the analog input is sampled at this
point. The conversion is also initiated at this point and will require
16 SCLK cycles to complete. The track-and-hold will go back into
track on the 14th SCLK falling edge as shown in Figures 17,
18,
and 19 at point B, except when the write is to the SHADOW
Register, in which case the track-and-hold will not return to track
until the rising edge of
CS
, i.e., point C in Figure 20.
On the 16th
SCLK falling edge, the DOUT line will go back into
three-
state. If the rising edge of
CS
occurs before 16 SCLKs have
elapsed, the conversion will be terminated, the DOUT line
will go back into three-state, and the Control Register will not
be updated; otherwise DOUT returns to three-state on the
16th
SCLK falling edge as shown in Figures
17, 18, and 19. Sixteen
serial clock cycles are required to perform
the conversion process
and to access data from the AD7908/AD7918/AD7928.
For
the AD7908/AD7918/AD7928 the 8/10/12 bits of data are
preceded by a leading zero and the three channel address
bits, ADD2 to ADD0, identify which channel the result corre-
sponds to.
CS
going low provides the leading zero to be
read in by the
microcontroller or DSP. The three remaining
address bits and data bits are then clocked out by subsequent
SCLK falling edges
beginning with the first address bit ADD2, thus
the first falling clock
edge on the serial clock has a leading zero
provided and also clocks
out address bit ADD2. The final bit in
the data transfer is valid on the
16th
falling edge, having been
clocked out on the previous (15th) falling edge.
Writing of information to the Control Register takes place on
the first 12 falling edges of SCLK in a data transfer, assuming
the MSB, i.e., the WRITE bit, has been set to 1. If the Control
Register is programmed to use the SHADOW Register, then
writing of information to the SHADOW Register will take place
on all 16 SCLK falling edges in the next serial transfer as shown
for example on the AD7928 in Figure 20. Two sequence options
can be programmed in the SHADOW Register. If the user does
not want to program a second sequence, then the eight LSBs
should be filled with zeros. The SHADOW Register will be
updated upon the rising edge of
CS
and the track-and-hold will
begin to track the first channel selected in the sequence.
The AD7908 will output a leading zero, three channel address
bits that the conversion result corresponds to, followed by the
8-bit conversion result, and four trailing zeros. The AD7918 will
output a leading zero, three channel address bits that the con-
version result corresponds to, followed by the 10-bit conversion
result, and two trailing zeros. The 16-bit word read from the
AD7928 will always contain a leading zero, three channel address
bits that the conversion result corresponds to, followed by the
12-bit conversion result.
MICROPROCESSOR INTERFACING
The serial interface on the AD7908/AD7918/AD7928 allows
the part to be directly connected to a range of many different
microprocessors. This section explains how to interface the
AD7908/AD7918/AD7928 with some of the more common
microcontroller and DSP serial interface protocols.
AD7908/AD7918/AD7928 to TMS320C541
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7908/AD7918/AD7928. The
CS
input allows easy interfacing
between the TMS320C541 and the AD7908/AD7918/AD7928
without any glue logic required. The serial port of the TMS320C541
is set up to operate in burst mode with internal CLKX0 (Tx serial
clock on serial port 0) and FSX0 (Tx frame sync from serial
port 0). The serial port control register (SPC) must have the
following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1.
The connection diagram is shown in Figure 21. It should be
noted that for signal processing applications, it is imperative that
the frame synchronization signal from the TMS320C541 provides
equidistant sampling. The V
DRIVE
pin of the AD7908/AD7918/
AD7928 takes the same supply voltage as that of the TMS320C541.
This allows the ADC to operate at a higher voltage than the
serial interface, i.e., TMS320C541, if necessary.
–21–
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