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參數(shù)資料
| 型號： | AD7908BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP |
| 中文描述： | 8-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | MO-153AC, TSSOP-20 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 607K |
| 代理商： | AD7908BRU |
AD7908/AD7918/AD7928
REV. A
TMS320C541
*
AD7908/
AD7918/
AD7928
*
CLKX
CLKR
DR
DT
FSX
FSR
V
DD
SCLK
DOUT
DIN
CS
V
DRIVE
*
ADDITIONAL PINS REMOVED FOR CLARITY
Figure 21. Interfacing to the TMS320C541
AD7908/AD7918/AD7928 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced directly to the
AD7908/AD7918/AD7928 without any glue logic required. The
V
DRIVE
pin of the AD7908/AD7918/AD7928 takes the same supply
voltage as that of the ADSP-218x. This allows the ADC to operate
at a higher voltage than the serial interface, i.e., ADSP-218x,
if necessary.
The SPORT0 control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1
The connection diagram is shown in Figure 22. The ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set as
an output and RFS set as an input. The DSP operates in Alternate
Framing mode and the SPORT control register is set up as
described. The frame synchronization signal generated on the TFS
is tied to
CS
and as with all signal processing applications equi-
distant sampling is necessary. However, in this example the timer
interrupt is used to control the sampling rate of the ADC, and
under certain conditions equidistant sampling may not be achieved.
AD7908/
AD7918/
AD7928
*
ADSP-218x
*
SCLK
DR
RFS
TFS
DT
V
DD
SCLK
DOUT
CS
DIN
V
DRIVE
*
ADDITIONAL PINS REMOVED FOR CLARITY
Figure 22. Interfacing to the ADSP-218x
The Timer Register, for example, is loaded with a value that will
provide an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and thus the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given (i.e., AX0 = TX0), the state of the SCLK is checked. The
DSP will wait until the SCLK has gone High, Low, and High
before transmission will start. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data may be transmitted or it
may wait until the next clock edge.
For example, if the ADSP-2189 had a 20 MHz crystal such that
it had a master clock frequency of 40 MHz, then the master cycle
time would be 25 ns. If the SCLKDIV register was loaded with
the value 3, then an SCLK of 5 MHz is obtained, and eight master
clock periods will elapse for every one SCLK period. Depending
on the throughput rate selected, if the timer register is loaded
with the value, say 803 (803 + 1 = 804), 100.5 SCLKs will occur
between interrupts and subsequently between transmit instruc-
tions. This situation will result in nonequidistant sampling as the
transmit instruction is occurring on a SCLK edge. If the number
of SCLKs between interrupts is a whole integer figure of N,
then equidistant sampling will be implemented by the DSP.
AD7908/AD7918/AD7928 to DSP563xx
The connection diagram in Figure 23 shows how the AD7908/
AD7918/AD7928 can be connected to the ESSI (Synchronous
Serial Interface) of the DSP563xx family of DSPs from Motorola.
Each ESSI (two on board) is operated in Synchronous mode
(SYN bit in CRB = 1) with internally generated word length
frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 = 0
in CRB). Normal operation of the ESSI is selected by making
MOD = 0 in the CRB. Set the word length to 16 by setting bits
WL1 = 1 and WL0 = 0 in CRA. The FSP bit in the CRB should
be set to 1 so the frame sync is negative. It should be noted that
for signal processing applications, it is imperative that the frame
synchronization signal from the DSP563xx provides equidis-
tant sampling.
In the example shown in Figure 23, the serial clock is taken from
the ESSI so the SCK0 pin must be set as an output, SCKD = 1.
The V
DRIVE
pin of the AD7908/AD7918/AD7928 takes the same
supply voltage as that of the DSP563xx. This allows the
ADC to operate at a higher voltage than the serial interface, i.e.,
DSP563xx, if necessary.
AD7908/
AD7918/
AD7928
*
DSP563xx
*
SCK
SRD
STD
SC2
V
DD
SCLK
DOUT
CS
DIN
V
DRIVE
*
ADDITIONAL PINS REMOVED FOR CLARITY
Figure 23. Interfacing to the DSP563xx
–23–
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