參數(shù)資料
型號(hào)： AD7910AKSZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT SRL 250KSPS SC70-6
標(biāo)準(zhǔn)包裝： 3,000
位數(shù)： 10
采樣率（每秒）： 250k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 15mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 6-TSSOP，SC-88，SOT-363
供應(yīng)商設(shè)備封裝： SC-70-6
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，單極
配用： EVAL-AD7910CBZ-ND - BOARD EVALUATION FOR AD7910
AD7910/AD7920
Rev. C | Page 17 of 24
VALID DATA
CS
SCLK
SDATA
110
12
14
16
AD7910/AD7920
02976-019
Figure 19. Normal Mode Operation
THREE-STATE
SDATA
SCLK
CS
110
12
14
16
2
02976-020
Figure 20. Entering Power-Down Mode
SCLK
CS
SDATA
THE PART
BEGINS TO
POWER UP
THE PART IS FULLY
POWERED UP WITH
VIN FULLY ACQUIRED
A
10
12
14
16
1
16
VALID DATA
INVALID DATA
02976-021
1
Figure 21. Exiting Power-Down Mode
When power supplies are first applied to the AD7910/AD7920, the
ADC can power up in either power-down mode or in normal
mode. Because of this, it is best to allow a dummy cycle to elapse to
ensure the part is fully powered up before attempting a valid
conversion. Likewise, if the intention is to keep the part in power-
down mode while not in use and the user wishes the part to power
up in power-down mode, the dummy cycle can be used to ensure
the device is in power-down mode by executing a cycle such as that
shown in Figure 20. Once supplies are applied to the
AD7910/AD7920, the power-up time is the same as that when
powering up from power-down mode. It takes approximately 1 μs
to power up fully if the part powers up in normal mode. It is not
necessary to wait 1 μs before executing a dummy cycle to ensure
the desired mode of operation.
Instead, the dummy cycle can occur directly after power is
supplied to the ADC. If the first valid conversion is performed
directly after the dummy conversion, care must be taken to
ensure that adequate acquisition time is allowed. As mentioned
earlier, when powering up from the power-down mode, the part
returns to track upon the first SCLK edge applied after the
falling edge of CS. However, when the ADC powers up initially
after supplies are applied, the track-and-hold is in track. This
means, assuming the user has the facility to monitor the ADC
supply current, if the ADC powers up in the desired mode of
operation and thus a dummy cycle is not required to change
mode then a dummy cycle is required to place the track-and-
hold into track.
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