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參數(shù)資料
| 型號： | AD7910ARM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70 |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 1091K |
| 代理商： | AD7910ARM |
REV. B
–4–
AD7910/AD7920
AD7920–SPECIFICATIONS
1
(continued)
AD7910/AD7920
Limit at T
MIN,
T
MAX
10
5
14 t
SCLK
16 t
SCLK
50
Parameter
f
SCLK2
Unit
kHz min
3
MHz max
Description
t
CONVERT
AD7910
AD7920
Minimum Quiet Time Required between Bus Relinquish and
Start of Next Conversion
Minimum
CS
Pulse Width
CS
to SCLK Setup Time
Delay from
CS
until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
V
DD
￡
3.3 V
3.3 V < V
DD
￡
3.6 V
V
DD
> 3.6 V
SCLK Falling Edge to SDATA Three-State
SCLK Falling Edge to SDATA Three-State
Power-Up Time from Full Power-Down
t
QUIET
ns min
t
1
t
2
t
34
t
44
t
5
t
6
t
75
10
10
22
40
0.4 t
SCLK
0.4
t
SCLK
ns min
ns min
ns max
ns max
ns min
ns min
10
9.5
7
36
See Note 7
1
ns min
ns min
ns min
ns max
ns min
m
s max
t
86
t
POWER-UP8
NOTES
1
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3
Minimum f
SCLK
at which specifications are guaranteed.
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when V
DD
= 2.35 V and 0.8 V or 2.0 V for V
DD
> 2.35 V.
5
Measured with a 50 pF load capacitor.
6
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the Timing Characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
7
t
7
values apply to t
8
minimum values also.
8
See Power-Up Time section.
Specifications subject to change without notice.
Parameter
A Grade
1, 2
B Grade
1, 2
Unit
Test Conditions/Comments
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Static)
2.35/5.25
2.35/5.25
V min/max
Digital I/Ps = 0 V or V
DD
V
DD
= 4.75 V to 5.25 V, SCLK On or Off
V
DD
= 2.35 V to 3.6 V, SCLK On or Off
V
DD
= 4.75 V to 5.25 V, f
SAMPLE
= 250 kSPS
V
DD
= 2.35 V to 3.6 V, f
SAMPLE
= 250 kSPS
Typically 50 nA
2.5
1.2
3
1.4
1
2.5
1.2
3
1.4
1
mA typ
mA typ
mA max
mA max
m
A max
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
7
Normal Mode (Operational)
15
4.2
5
3
15
4.2
5
3
mW max
mW max
m
W max
m
W max
V
DD
= 5 V, f
SAMPLE
= 250 kSPS
V
DD
= 3 V, f
SAMPLE
= 250 kSPS
V
DD
= 5 V
V
DD
= 3 V
Full Power-Down
NOTES
1
Temperature range from –40
∞
C to +85
∞
C.
2
Operational from V
DD
= 2.0 V, with input low voltage (V
INL
) 0.35 V max.
3
See Terminology section.
4
B Grade, maximum specs apply as typical figures when V
DD
= 4.75 V to 5.25 V.
5
SC70 values guaranteed by characterization.
6
Guaranteed by characterization.
7
See Power vs. Throughput Rate section.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1
(
V
DD
= 2.35 V to 5.25 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
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