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參數(shù)資料
| 型號： | AD7918BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | MO-153AC, TSSOP-20 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 607K |
| 代理商： | AD7918BRU |
AD7908/AD7918/AD7928
REV. A
CS
SCLK
DOUT
DIN
1
14
16
1
14
16
PART IS IN FULL
SHUTDOWN
PART BEGINS TO POWER UP ON
CS
RISING EDGE AS PM1 = PM0 = 1
THE PART IS FULLY POWERED UP
ONCE
t
POWER UP
HAS ELAPSED
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS. PM1 = 1, PM0 = 1
TO KEEP THE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA IN TO CONTROL REGISTER
DATA IN TO CONTROL/SHADOW REGISTER
t
12
Figure 13. Full Shutdown Mode Operation
1
CS
SCLK
DOUT
DIN
16
1
16
1
16
DUMMY CONVERSION
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA IN TO CONTROL/SHADOW REGISTER
PART ENTERS
SHUTDOWN ON
CS
RISING EDGE AS
PM1 0, PM0 1
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS, PM1 0, PM0 1
DATA IN TO CONTROL/SHADOW REGISTER
CONTROL REGISTER CONTENTS SHOULD
NOT CHANGE, WRITE BIT 0
TO KEEP PART IN THIS MODE, LOAD PM1 0, PM0 1 IN
CONTROL REGISTER OR SET WRITE BIT = 0
PART IS FULLY
POWERED UP
PART BEGINS TO
POWER
UP ON
CS
FALLING EDGE
PART ENTERS
SHUTDOWN ON
CS
RISING EDGE AS
PM1 0, PM0 1
12
12
12
Figure 14. Auto Shutdown Mode Operation
1
CS
SCLK
DOUT
DIN
16
1
16
1
16
DUMMY CONVERSION
INVALID DATA
DATA IN TO CONTROL REGISTER
CORRECT VALUE IN CONTROL
REGISTER, VALID DATA FROM
NEXT CONVERSION, USER CAN
WRITE TO SHADOW REGISTER
IN NEXT CONVERSION
KEEP DIN LINE TIED HIGH FOR FIRST TWO DUMMY CONVERSIONS
CONTROL REGISTER IS LOADED ON THE FIRST
12 CLOCK EDGES
12
12
12
DUMMY CONVERSION
INVALID DATA
INVALID DATA
Figure 15. Placing AD7928 into the Required Operating Mode after Supplies are Applied
POWER VS. THROUGHPUT RATE
By operating in Auto Shutdown mode on the AD7908/AD7918/
AD7928, the average power consumption of the ADC decreases
at lower throughput rates. Figure 16 shows how as the through-
put rate is reduced, the part remains in its shutdown state longer
and the average power consumption over time drops accordingly.
For example if the AD7928 is operated in a continuous sam-
pling mode, with a throughput rate of 100 kSPS and an SCLK
of 20 MHz (AV
DD
= 5 V), and the device is placed in Auto
Shutdown mode, i.e., if PM1 = 0 and PM0 = 1, then the power
consumption is calculated as follows:
The maximum power dissipation during normal operation is
13.5 mW (AV
DD
= 5 V). If the power-up time from Auto Shutdown
is one dummy cycle, i.e., 1 μs, and the remaining conversion
time is another cycle, i.e., 1 μs, then the AD7928 can be said
to dissipate 13.5 mW for 2 μs during each conversion cycle.
For the remainder of the conversion cycle, 8 μs, the part
remains in Auto Shutdown mode. The AD7928 can be said
to dissipate 2.5 μW for the remaining 8 μs of the conversion
cycle. If the throughput rate is 100 kSPS, the cycle time is 10 μs
and the average power dissipated during each cycle is
(2/10) (13.5 mW) + (8/10) (2.5 μW) = 2.702 mW.
Figure 16 shows the maximum power versus throughput rate
when using the Auto Shutdown mode with 3 V and 5 V supplies.
–20–
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