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參數(shù)資料
| 型號： | AD7920BRM-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70 |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 1091K |
| 代理商： | AD7920BRM-REEL7 |
REV. B
AD7910/AD7920
–15–
SERIAL INTERFACE
Figures 13 and 14 show the detailed timing diagram for serial
interfacing to the AD7920 and AD7910, respectively. The serial
clock provides the conversion clock and also controls the transfer
of information from the AD7910/AD7920 during conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at that point. The conversion is also initiated at this point.
For the AD7920, the conversion requires 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, track-and-
hold goes back into track on the next SCLK rising edge as shown
in Figure 13 at point B. On the 16th SCLK falling edge, the
SDATA line goes back into three-state. If the rising edge of
CS
occurs before 16 SCLKs have elapsed, then the conversion is
terminated and the SDATA line goes back into three-state;
otherwise, SDATA returns to three-state on the 16th SCLK
falling edge, as shown in Figure 13. Sixteen serial clock cycles
are required to perform the conversion process and to access data
from the AD7920.
For the AD7910, the conversion requires 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, track-and-
hold goes back into track on the next SCLK rising edge, as shown
in Figure 14 at point B.
If the rising edge of
CS
occurs before 14 SCLKs have elapsed,
the conversion is terminated and the SDATA line goes back into
three-state. If 16 SCLKs are used in the cycle, SDATA returns to
three-state on the 16th SCLK falling edge, as shown in Figure 14.
CS
going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the sec-
ond leading zero. Thus the first falling clock edge on the serial
clock has the first leading zero provided and also clocks out the
second leading zero. The final bit in the data transfer is valid on
the 16th falling edge, having being clocked out on the previous
(15th) falling edge.
In applications with a slower SCLK, it is possible to read in data on
each SCLK rising edge. In this case, the first falling edge of SCLK
will clock out the second leading zero, which could be read in the
first rising edge. However, the first leading zero that was clocked
out when
CS
went low will be missed unless it was not read in
the first falling edge. The 15th falling edge of SCLK will clock
out the last bit and it could be read in the 15th rising SCLK edge.
If
CS
goes low just after the SCLK falling edge has elapsed,
CS
clocks out the first leading zero as before, and it may be read on the
SCLK rising edge. The next SCLK falling edge clocks out the second
leading zero and it could be read on the following rising edge.
CS
SCLK
SDATA
t
2
t
6
t
3
t
4
ZERO
t
7
DB10
t
5
t
8
t
CONVERT
t
QUIET
ZERO
ZERO
DB11
DB2
DB1
DB0
B
THREE-STATE
THREE-
STATE
Z
4 LEADING ZEROS
1
2
3
4
5
13
14
15
16
t
1
1/THROUGHPUT
Figure 13. AD7920 Serial Interface Timing Diagram
SCLK
1
5
13
15
4 LEADING ZEROS
THREE-STATE
t
4
2
3
4
16
t
5
t
3
t
2
DB9
DB8
DB0
ZERO
6
t
7
t
8
14
ZERO
ZERO
ZERO
Z
t
1
ZERO
2 TRAILING ZEROS
SDATA
t
QUIET
B
THREE-STATE
CS
t
CONVERT
1/THROUGHPUT
Figure 14. AD7910 Serial Interface Timing Diagram
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