參數(shù)資料
型號： AD7921ARM-REEL7
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs
中文描述： 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝： MO-187AA, MSOP-8
文件頁數(shù)： 8/28頁
文件大?。?/td> 312K
代理商： AD7921ARM-REEL7
AD7911/AD7921
TIMING EXAMPLES
Figure 6 and Figure 7 show some of the timing parameters from
the Timing Specifications section.
Timing Example 1
As shown in Figure 7, when
f
SCLK
= 5 MHz and the throughput is
250 kSPS, the cycle time is
Rev. 0 | Page 8 of 28
t
2
+ 12.5(1/
f
SCLK
) +
t
ACQ
= 4 μs
With
t
2
= 10 ns minimum, then
t
ACQ
is 1.49 μs, which satisfies
the requirement of 290 ns for
t
ACQ
.
In Figure 7,
t
ACQ
is comprised of 2.5(1/
f
SCLK
) +
t
10
+
t
QUIET
, where
t
10
= 30 ns maximum. This allows a value of 960 ns for
t
QUIET
,
satisfying the minimum requirement of 30 ns.
Timing Example 2
The AD7921 can also operate with slower clock frequencies. As
shown in Figure 7, when
f
SCLK
= 2 MHz and the throughput rate
is 100 KSPS, the cycle time is
t
2
+ 12.5(1/
f
SCLK
) +
t
ACQ
= 10 μs
With
t
2
= 10 ns minimum, then
t
ACQ
is 3.74 μs, which satisfies
the requirement of 290 ns for t
ACQ
.
In Figure 7,
t
ACQ
is comprised of 2.5(1/
f
SCLK
) +
t
10
+
t
QUIET
, where
t
10
= 30 ns maximum. This allows a value of 2.46 μs for
t
QUIET
,
satisfying the minimum requirement of 30 ns.
In this example, as with other slower clock values, the signal
might already be acquired before the conversion is complete,
but it is still necessary to leave 30 ns minimum
t
QUIET
between
conversions. In this example, the signal should be fully acquired
at approximately point C in Figure 7.
0
ZERO
X
1
2
3
4
5
13
14
t
5
15
16
X
CHN
X
X
X
X
X
X
CHN
X
DB11
DB10
DB2
DB1
DB0
Z
t
2
t
6
t
4
t
8
t
9
t
3
t
7
t
10
t
1
t
QUIET
t
CONVERT
SCLK
CS
DOUT
THREE-STATE
THREE-STATE
DIN
B
Figure 6. AD7921 Serial Interface Timing Diagram
0
1
2
3
4
5
13
14
15
t
10
16
t
QUIET
t
ACQUISITION
1/THROUGHPUT
12.5(1/f
SCLK
)
t
CONVERT
B
C
SCLK
CS
t
2
Figure 7. Serial Interface Timing Example
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