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參數(shù)資料
| 型號： | AD7921ARM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 312K |
| 代理商： | AD7921ARM |
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AD7911/AD7921
Table 7 provides some typical performance data with various
op amps used as the input buffer, and a 50 kHz input tone under
the same setup conditions.
Table 7. AD7921 Performance for Various Input Buffers
Op Amp in the Input
Buffer
50 kHz Input , V
DD
= 3.6 V
Single op amps
AD8038
72.79
AD8510
72.35
AD8021
72.2
Dual op amps
AD712
72.68
AD8022
72.88
Rev. 0 | Page 17 of 28
AD7921 SNR Performance (dB)
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases and performance degrades (see
Figure 16).
DIGITAL INPUTS
The digital inputs applied to the AD7911/AD7921 are not
limited by the maximum ratings that limit the analog input.
Instead, the digital inputs applied can go to 7 V and are not
restricted by the V
DD
+ 0.3 V limit as on the analog input. For
example, if the AD7911/AD7921 are operated with a V
DD
of 3 V,
then 5 V logic levels could be used on the digital inputs. How-
ever, it is important to note that the data output on DOUT still
has 3 V logic levels when V
DD
= 3 V. Another advantage of
SCLK, DIN, and CS not being restricted by the V
DD
+ 0.3 V limit
is that power supply sequencing issues are avoided. If CS, DIN,
or SCLK are applied before V
DD
, then there is no risk of latch-up
as there would be on the analog inputs, if a signal greater than
0.3 V were applied prior to V
DD
.
DIN INPUT
The channel to be converted on in the next conversion is
selected by writing to the DIN pin. Data on the DIN pin is
loaded into the AD7911/AD7921 on the falling edge of SCLK.
The data is transferred into the part on the DIN pin at the same
time that the conversion result is read from the part.
Only the third bit of the DIN word is used; the rest are ignored
by the ADC. The third MSB is the channel identifier bit, which
identifies the channel to be converted on in the next conversion,
V
IN0
(CHN = 0) or V
IN1
(CHN = 1).
0
LSB
MSB
X
X
CHN
X
DON'T CARE
Figure 24. AD7911/AD7921 DIN Word
DOUT OUTPUT
The conversion result from the AD7911/AD7921 is provided on
this output as a serial data stream. The bits are clocked out on
the SCLK falling edge at the same time that the conversion is
taking place.
The serial data stream for the AD7921 consists of two leading
zeros followed by the bit that identifies the channel converted,
an invalid bit that matches up to the channel identifier bit, and
the 12-bit conversion result with MSB provided first.
For the AD7911, the serial data stream consists of two leading
zeros followed by the bit that identifies the channel converted,
an invalid bit that matches up to the channel identifier bit, and
the 10-bit conversion result with MSB provided first, followed
by two trailing zeros.
0
LSB
AD7911
MSB
0
0
0
0
CHN
X
CONVERSION RESULT
AD7921
0
0
CHN
X
CONVERSION RESULT
Figure 25. AD7911/AD7921 DOUT Word
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