參數(shù)資料
型號(hào)： AD7934BRU
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/32頁(yè)
文件大小： 0K
描述： IC ADC 12BIT 4CH 1.5MSPS 28TSSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 12
采樣率（每秒）： 1.5M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 13.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 管件
輸入數(shù)目和類型： 4 個(gè)單端，單極；2 個(gè)差分，單極；2 個(gè)偽差分，單極
AD7933/AD7934
Rev. B | Page 27 of 32
POWER vs. THROUGHPUT RATE
A considerable advantage of powering the ADC down after a
conversion is that the power consumption of the part is
significantly reduced at lower throughput rates. When using the
different power modes, the AD7933/AD7934 are only powered
up for the duration of the conversion. Therefore, the average
power consumption per cycle is significantly reduced. Figure 39
shows a plot of power vs. throughput rate when operating in
autostandby mode for both VDD = 5 V and 3 V. For example, if
the device runs at a throughput rate of 10 kSPS, the overall cycle
time is 100 μs. If the maximum CLKIN frequency of 25.5 MHz
is used, the conversion time accounts for only 0.525 μs of the
overall cycle time while the AD7933/AD7934 remains in
standby mode for the remainder of the cycle.
Figure 40 shows a plot of the power vs. the throughput rate
when operating in normal mode for both VDD = 5 V and 3 V.
In both plots, the figures apply when using the internal
reference. If an external reference is used, the power-up time
reduces to 600 ns; therefore, the AD7933/AD7934 remains in
standby for a greater time in every cycle. Additionally, the
current consumption, when converting, should be lower than
the specified maximum of 2.7 mA with VDD = 5 V, or 2.0 mA
with VDD = 3 V, respectively.
THROUGHPUT (kSPS)
P
O
WE
R
(
m
W)
1.8
0.8
1.0
1.2
1.4
1.6
0
0.6
0.4
0.2
0
20
406080
100
120
140
TA = 25°C
VDD =5V
VDD =3V
03
71
3-
0
42
Figure 39. Power vs. Throughput in
Autostandby Mode Using Internal Reference
THROUGHPUT (kSPS)
P
O
WE
R
(
m
W)
10
4
5
6
7
8
9
0
3
2
1
0
200
400
600
800
1000
1200
1600
1400
TA = 25°C
VDD =5V
VDD =3V
03
71
3-
0
43
Figure 40. Power vs. Throughput in Normal Mode Using Internal Reference
MICROPROCESSOR INTERFACING
AD7933/AD7934 to ADSP-21xx Interface
Figure 41 shows the AD7933/AD7934 interfaced to the
ADSP-21xx series of DSPs as a memory-mapped device.
A single wait state may be necessary to interface the AD7933/
AD7934 to the ADSP-21xx, depending on the clock speed of
the DSP. The wait state can be programmed via the data memory
wait state control register of the ADSP-21xx (see the ADSP-21xx
family User’s Manual for details). The following instruction
reads from the AD7933/AD7934:
MR = DM (ADC)
where ADC is the address of the AD7933/AD7934.
AD7933/
AD7934*
ADSP-21xx*
WR
RD
DB0 TO DB11
D0 TO D23
A0 TO A15
DMS
IRQ2
BUSY
CS
CONVST
DSP/USER SYSTEM
WR
RD
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
DATA BUS
ADDRESS
DECODER
03
71
3-
0
44
Figure 41. Interfacing to the ADSP-21xx
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