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參數(shù)資料
| 型號： | AD7942BCPWP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 250 kSPS PulSAR ADC in MSOP/QFN |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, DSO10 |
| 封裝： | 3 X 3 MM, QFN-10 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大小： | 633K |
| 代理商： | AD7942BCPWP |
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AD7942
Preliminary Technical Data
Rev Pr B | Page 20 of 28
CS Mode 3-Wire with BUSY Indicator
This mode is usually used when a single AD7942 is connected
to an SPI compatible digital host having an interrupt input.
The connection diagram is shown in Figure 31 and the
corresponding timing is given in Figure 32.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion is
complete, SDO goes from high impedance to low. With a pull-
up on the SDO line, this transition can be used as an interrupt
signal to initiate the data reading controlled by the digital host.
The AD7942 then enters the acquisition phase and powers
down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge will allow a faster
reading rate provided it has an acceptable hold time. After the
optional 15th SCK falling edge, or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDO
SDI
DATA IN
IRQ
CLK
CONVERT
VIO
DIGITAL HOST
AD7942
47k
Figure 31. CS Mode 3-Wire with BUSY Indicator
Connection Diagram (SDI High)
04656-P
rC-010
SDO
D13
D12
D1
D0
tDIS
SCK
1
2
3
13
14
15
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
tCNVH
tACQ
ACQUISITION
SDI = 1
Figure 32. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
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| AD7942BCPZRL | 功能描述:IC ADC 14BIT SAR 250KSPS 10LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7942BCPZRL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/QFN |
| AD7942BCPZRL7 | 功能描述:IC ADC 14BIT 250KSPS 10-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7942BCPZRL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/QFN |
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