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參數(shù)資料
| 型號： | AD7942BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 250 kSPS PulSAR ADC in MSOP/QFN |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 633K |
| 代理商： | AD7942BRM |
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AD7942
Preliminary Technical Data
Rev Pr B | Page 24 of 28
Chain Mode with BUSY Indicator
This mode can also be used to daisy chain multiple AD7942s on
a 3-wire serial interface while providing a BUSY indicator. This
feature is useful for reducing component count and wiring
connections, e.g., in isolated multiconverter applications or for
systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7942s is shown
in Figure 39 and the corresponding timing is given in Figure 40.
When SDI and CNV are low, SDO is driven low. With SCK high,
a rising edge on CNV initiates a conversion, selects the chain
mode, and enables the BUSY indicator feature. In this mode,
CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the nearend ADC ( ADC C in
Figure 39) SDO will be driven high. This transition on SDO can
be used as a BUSY indicator to trigger the data readback
controlled by the digital host. The AD7942 then enters the
acquisition phase and powers down. The data bits stored in the
internal shift register are then clocked out, MSB first, by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 14 × N + 1 clocks are required to readback the N ADCs.
Although the rising edge can be used to capture the data, a
digital host also using the SCK falling edge will allow a faster
reading rate and, consequently more AD7942s in the chain,
provided the digital host has an acceptable hold time. For
instance, with a 5 ns digital host set-up time and 3 V interface,
up to six AD7942s running at a conversion rate of 250 kSPS can
be daisy-chained to a single 3-wire port.
CNV
SCK
SDO
SDI
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
AD7942
C
CNV
SCK
SDO
SDI
AD7942
B
CNV
SCK
SDO
SDI
AD7942
A
Figure 39. Chain Mode with BUSY Indicator Connection Diagram
04656-P
rC-018
SDOA = SDIB
DA13 DA12 DA11
SCK
12
3
35
41
42
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV = SDIA
DA1
413
tSCK
tSCKH
tSCKL
DA0
15
31
13
SDOB = SDIC
DB13 DB12 DB11
DA1
DB1DB0DA13 DA12
43
tSSDISCK
tHSDISC
tHSDO
tDSDO
SDOC
DC13 DC12 DC11
DA1DA0
DC1DC0DA12
17
27
28
16
29
DB1DB0DA13
DB13 DB12
tDSDOSDI
tSSCKCNV
tHSCKCNV
DA0
Figure 40. Chain Mode with BUSY Indicator Serial Interface Timing
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