參數(shù)資料
型號(hào): AD7942BRMRL7
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 14-Bit, 250 kSPS PulSAR ADC in MSOP/QFN
中文描述: 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10
封裝: MO-187BA, MSOP-10
文件頁數(shù): 11/28頁
文件大小: 633K
代理商: AD7942BRMRL7
Preliminary Technical Data
AD7942
Rev Pr B | Page 19 of 28
CS MODE 3-Wire, No BUSY Indicator
This mode is usually used when a single AD7942 is connected
to an SPI compatible digital host. The connection diagram is
shown in Figure 29 and the corresponding timing is given in
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it will continue to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7942
enters the acquisition phase and powers down. When CNV goes
low, the MSB is output onto SDO. The remaining data bits are
then clocked by subsequent SCK falling edges. The data is valid
on both SCK edges. Although the rising edge can be used to
capture the data, a digital host also using the SCK falling edge
will allow a faster reading rate provided it has an acceptable
hold time. After the 14th SCK falling edge or when CNV goes
high, whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDO
SDI
DATA IN
CLK
CONVERT
VIO
DIGITAL HOST
AD7942
Figure 29. CS Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
04656-P
rC-008
SDO
D13
D12
D11
D1
D0
tDIS
SCK
1
2
3
12
13
14
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
Figure 30. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
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