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參數(shù)資料
| 型號(hào)： | AD7980ARMZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 13/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | ADC 16BIT 1MSPS 2.5LSB 10-MSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 10mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)偽差分，單極 |
| 產(chǎn)品目錄頁(yè)面： | 780 (CN2011-ZH PDF) |
| 其它名稱： | AD7980ARMZRL7DKR |
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AD7980
Data Sheet
Rev. C | Page 20 of 28
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7980 is connected
to an SPI-compatible digital host that has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the
data reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 37, and the
corresponding timing is given in Figure 38.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high impedance
to low.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7980 then enters the acquisition phase
and powers down. The data bits are clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge or SDI going high, whichever is earlier,
the SDO returns to high impedance.
06392-
021
AD7980 SDO
SDI
DATA IN
IRQ
DIGITAL HOST
CONVERT
CS1
CLK
VIO
47kΩ
CNV
SCK
Figure 37. 4-Wire CS Mode with Busy Indicator Connection Diagram
06392-
022
tCONV
tCYC
AQUISITION
tSSDICNV
AQUISITION
tACQ
tSCK
tSCKH
tSCKL
CONVERSION
SDI
tHSDICNV
SCK
CNV
SDO
tEN
D15
D14
D1
D0
tHSDO
1
2
3
15
16
17
tDSDO
tDIS
Figure 38. 4-Wire CS Mode with Busy Indicator Serial Interface Timing
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