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參數(shù)資料
| 型號： | AD7983BRMZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 1.33MSPS 10MSOP |
| 標準包裝： | 1,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1.33M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
AD7983
Rev. A | Page 17 of 24
When CNV goes low, the MSB is output onto SDO. The
remaining data bits are then clocked by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate provided that it has an
acceptable hold time. After the 16th SCK falling edge or when
CNV goes high, whichever is earlier, SDO returns to high
impedance.
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7983 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 26, and the corresponding timing is given in
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. When a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for example, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held
high for the maximum conversion time to avoid the generation
of the busy signal indicator. When the conversion is complete, the
AD7983 enters the acquisition phase and goes into standby mode.
AD7983 SDO
SDI
DATA IN
DIGITAL HOST
CONVERT
CLK
VIO
CNV
SCK
06
97
4-
01
2
Figure 26. CS Mode, 3-Wire Without Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCNVH
tCONV
tCYC
CNV
ACQUISITION
tACQ
tSCK
tSCKL
CONVERSION
SCK
SDO
D15
D14
D13
D1
D0
tEN
tHSDO
1
2
3
14
15
16
tDSDO
tDIS
tSCKH
06
97
4-
0
13
Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
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