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參數(shù)資料
| 型號(hào)： | AD7993BRU-1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 4CHAN I2C 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 188k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.2mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD7993/AD7994
Rev. 0 | Page 30 of 32
9
11
A
9
S
WA
A
Sr
RA
A
SECOND DATA BYTE
(LSBs)
FIRST DATA BYTE
(MSBs)
COMMAND/ADDRESS
POINT BYTE
7-BIT ADDRESS
SDA
11
9
SCL
SDA
SCL
9
Sr/P
8
ACK BY
AD7993/AD7994
ACK BY
AD7993/AD7994
ACK BY
MASTER
NACK BY
MASTER
ACK BY
AD7993/AD7994
03472-0-033
A
Figure 33. Mode 2 Operation
9
11
SCL
9
S
7-BIT ADDRESS
WA
COMMAND/ADDRESS
POINT BYTE
A
SDA
FIRST DATA BYTE
(MSBs)
A
SECOND DATA BYTE
(LSBs)
FIRST DATA BYTE
(MSBs)
SECOND DATA BYTE
(LSBs)
A
Sr
7-BIT ADDRESS
RA
SDA
9
1
SCL
9
8
ACK BY
AD7993/AD7994
ACK BY
AD7993/AD7994
ACK BY
MASTER
ACK BY
MASTER
ACK BY
MASTER
ACK BY
AD7993/AD7994
A
9
RESULT FROM CH1
RESULT FROM CH2
A/A
03472-0-034
Figure 34. Mode 2 Sequence Operation
MODE 3—AUTOMATIC CYCLE INTERVAL MODE
An automatic conversion cycle can be selected and enabled by
writing a value to the cycle timer register. A conversion cycle
interval can be set up on the AD7993/AD7994 by programming
the relevant bits in the 8-bit cycle timer register, as decoded in
Table 25. Only the 3 LSB are used; the 5 MSB should contain 0s.
When the 3 LSB of the register are programmed with any
configuration other than all 0s, a conversion takes place every
X ms; the cycle interval, X, depends on the configuration of
these three bits in the cycle timer register. There are seven
different cycle time intervals to choose from, as shown in
Table 25. Once the conversion takes place, the part powers
down again until the next conversion. To exit this mode of
operation, the user must program the 3 LSB of the cycle timer
register to contain all 0s. To select a channel(s) for operation in
the cycle mode, set the corresponding channel bit(s), D7 to D4,
of the configuration register. If more than one channel bit is set
in the configuration register, the ADC automatically cycles
through the channel sequence starting with the lowest channel
and working its way up through the sequence. Once the
sequence is complete, the ADC starts converting on the lowest
channel again, continuing to loop through the sequence until
the cycle timer register’s contents are set to all 0s. This mode
is useful for monitoring signals such as battery voltage, and
temperature, alerting only when the limits are violated.
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