參數(shù)資料
型號(hào): AD8003ACPZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 14/17頁(yè)
文件大?。?/td> 0K
描述: IC OPAMP CF TRPL LDIST 24LFCSP
標(biāo)準(zhǔn)包裝: 1
放大器類型: 電流反饋
電路數(shù): 3
轉(zhuǎn)換速率: 3800 V/µs
-3db帶寬: 1.65GHz
電流 - 輸入偏壓: 7µA
電壓 - 輸入偏移: 700µV
電流 - 電源: 9.5mA
電流 - 輸出 / 通道: 100mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 10 V,±2.25 V ~ 5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 24-LFCSP-VQ(4x4)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 769 (CN2011-ZH PDF)
配用: EVAL-AD8003-3CPEZ-ND - BOARD EVALUATION AD8003-3CPEZ
其它名稱: AD8003ACPZ-REEL7DKR
Data Sheet
AD8003
Rev. C | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
11 V
Power Dissipation
Common-Mode Input Voltage
VS 0.7 V to +VS + 0.7 V
Differential Input Voltage
±VS
Exposed Paddle Voltage
VS
Storage Temperature Range
65°C to +125°C
Operating Temperature Range
40°C to +85°C
Lead Temperature (Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
Unit
24-Lead LFCSP_WQ
70
°C/W
Maximum Power Dissipation
The maximum safe power dissipation for the AD8003 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the AD8003. Exceeding a junction temperature of 175°C for
an extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the AD8003 drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
PD = Quiescent Power + (Total Drive Power – Load Power)
(
)
L
2
OUT
L
OUT
S
D
R
V
R
V
2
V
I
V
P
×
+
×
=
RMS output voltages should be considered. If RL is referenced to
VS, as in single-supply operation, the total drive power is VS ×
IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
(
) (
)
L
S
D
R
/
V
I
V
P
2
4
+
×
=
In single-supply operation with RL referenced to VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
In addition, more metal directly in contact with the package
leads and exposed paddle from metal traces, through holes,
ground, and power planes reduce θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle,
4 mm × 4 mm LFCSP_WQ (70°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
05721-
037
0
3.0
–55
125
AMBIENT TEMPERATURE (°C)
MA
XI
MU
M
PO
W
ER
D
ISSI
PA
T
IO
N
(W
)
0.5
1.0
1.5
2.0
2.5
–35
–15
5
25
45
65
85
105
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
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