參數(shù)資料
型號: AD8007AR-REEL
廠商: Analog Devices Inc
文件頁數(shù): 10/21頁
文件大?。?/td> 0K
描述: IC OPAMP CF ULDIST LN LP 8SOIC
標準包裝: 2,500
放大器類型: 電流反饋
電路數(shù): 1
轉換速率: 1000 V/µs
-3db帶寬: 650MHz
電流 - 輸入偏壓: 4µA
電壓 - 輸入偏移: 500µV
電流 - 電源: 9mA
電流 - 輸出 / 通道: 130mA
電壓 - 電源,單路/雙路(±): 5 V ~ 12 V,±2.5 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SO
包裝: 帶卷 (TR)
AD8007/AD8008
Rev. E | Page 17 of
20
LAYOUT AND GROUNDING CONSIDERATIONS
GROUNDING
A ground plane layer is important in densely packed printed
circuit boards (PCB) to minimize parasitic inductances. However,
an understanding of where the current flows in a circuit is critical
to implementing effective high speed circuit design. The length
of the current path is directly proportional to the magnitude of
parasitic inductances and thus the high frequency impedance of
the path. High speed currents in an inductive ground return
create unwanted voltage noise. Broad ground plane areas reduce
parasitic inductance.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
Even 1 pF or 2 pF of capacitance reduces the input impedance at
high frequencies, in turn increasing the gain of the amplifier, which
causes peaking of the frequency response or even oscillations if
severe enough. Place the external passive components that are
connected to the input pins as close as possible to the inputs to
avoid parasitic capacitance. The ground and power planes must
be kept at a distance of at least 0.05 mm from the input pins on
all layers of the board.
OUTPUT CAPACITANCE
To a lesser extent, parasitic capacitances on the output can cause
peaking of the frequency response. The following two methods
minimize its effect:
Put a small value resistor in series with the output to isolate
the load capacitance from the output stage of the amplifier
(see Figure 12).
Increase the phase margin by increasing the gain of the
amplifier or by increasing the value of the feedback resistor.
INPUT-TO-OUTPUT COUPLING
To minimize capacitive coupling, the input and output signal
traces should not be parallel. When they are not parallel, they
help reduce unwanted positive feedback.
EXTERNAL COMPONENTS AND STABILITY
The AD8007/AD8008 are current feedback amplifiers and, to a
first order, the feedback resistor determines the bandwidth and
stability. The gain, load impedance, supply voltage, and input
impedances also have an effect.
Figure 11 shows the effect of changing RF on the bandwidth and
peaking for a gain of 2. Increasing RF reduces peaking but also
reduces bandwidth. Figure 6 shows that for a given RF increasing
the gain also reduces peaking and bandwidth. Table 4 shows the
recommended RF and RG values that optimize bandwidth with
minimal peaking.
Table 4. Recommended Component Values
Gain
RF (Ω)
RG (Ω)
RS (Ω)
1
499
200
+1
499
Not applicable
200
+2
499
200
+5
499
124
200
+10
499
54.9
200
The load resistor also affects bandwidth, as shown in Figure 7 and
Figure 10. A comparison between Figure 7 and Figure 10 also
demonstrates the effect of gain and supply voltage.
When driving loads with a capacitive component, stability
improves by using a series snub resistor, RSNUB, at the output.
The frequency and pulse responses for various capacitive
loads are illustrated in Figure 12 and Figure 47, respectively.
For noninverting configurations, a resistor in series with the
input, RS, is needed to optimize stability for a gain of 1, as
illustrated in Figure 8. For larger noninverting gains, the effect
of a series resistor is reduced.
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