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參數資料
| 型號： | AD8018ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 2/19頁 |
| 文件大小： | 0K |
| 描述： | IC LINE DRIVER XDSL R-R 8SOIC |
| 標準包裝： | 2,500 |
| 類型： | 驅動器 |
| 驅動器/接收器數： | 2/0 |
| 規(guī)程： | xDSL |
| 電源電壓： | 3.3 V ~ 8 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 配用： | AD8018ARU-EVAL-ND - BOARD EVAL FOR AD8018 AD8018AR-EVAL-ND - BOARD EVAL FOR AD8018 |
REV. A
AD8018
–10–
P
V rmsV
V rms
R
IV
P
TOT
O
S
O
L
Q
S
OUT
=×
+
40 8
1
2
(.
–
)
α
For the AD8018, operating on a single 5 V supply and deliver-
ing a total of 16 dBm (13 dBm to the line and 3 dBm to the
matching network) into 12.5
(100 reflected back through
a 1:4.0 transformer plus back termination), the power is:
= 261 mW + 40 mW
= 301 mW
Using these calculations, and a
θJA of 115°C/W for the TSSOP
package and 100
°C/W for the SOIC, Tables III and IV show
junction temperature versus power delivered to the line for sev-
eral supply voltages.
Table III. Junction Temperature vs. Line Power and
Operating Voltage for TSSOP, TAMB = 85 C
VSUPPLY
PLINE, dBm 5
6
7
8
13
115
122
129
136
14
117
125
132
140
15
119
127
136
144
16
121
130
139
148
17
123
133
143
153
18
125
136
147
158
Table IV. Junction Temperature vs. Line Power and
Operating Voltage for SOIC, TAMB = 85 C
VSUPPLY
PLINE, dBm
5
6
7
8
13
111
117
123
129
14
113
119
126
133
15
115
122
129
136
16
116
124
132
140
17
118
127
136
144
18
120
130
139
149
Running the AD8018 at voltages near 8 V can produce junction
temperatures that exceed the thermal rating of the TSSOP pack-
ages and should be avoided. The shaded areas indicate junction
temperatures greater than 150
°C.
LAYOUT CONSIDERATIONS
As is the case with all high-speed applications, careful attention
to printed circuit board layout details will prevent associated
board parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the board
to provide a low-impedance return path. Removing the ground
plane on all layers from the area near the input and output pins
will reduce stray capacitance, particularly in the area of the
inverting inputs. Signal lines connecting the feedback and gain
resistors should be as short as possible to minimize the inductance
and stray capacitance associated with these traces. Termination
resistors and loads should be located as close as possible to their
respective inputs and outputs. Input and output traces should
be kept as far apart as possible to minimize coupling (crosstalk)
though the board. Adherence to stripline design techniques for
long signal traces (greater than about 1 inch) is recommended.
This circuit requires significant power supply bypassing. The
AD8018 operates on a split supply in this circuit. The bypassing
technique shown in TPC 13 utilizes a 220
F tantalum capacitor
and a 0.1
F ceramic chip capacitor in parallel, connected from
the positive to negative supply, and a 10
F tantalum and 0.1 F
ceramic chip capacitor in parallel, connected from each supply to
ground. The capacitors connected between the power supplies
serve to minimize any voltage ripples that might appear at the
supplies while sourcing or sinking any large differential current.
The large capacitor has a pool of charge instantly available for
the AD8018 to draw from, thus preventing any erroneous dis-
tortion results.
POWER DISSIPATION
It is important to consider the total power dissipation of the
AD8018 in order to properly size the heat sink area of an
application. Figure 8 is a simple representation of a differential
driver. With some simplifying assumptions we can estimate the
total power dissipated in this circuit. If the output current is
large compared to the quiescent current, computing the dissipa-
tion in the output devices and adding it to the quiescent power
dissipation will give a close approximation of the total power
dissipation in the package. A factor
α (~0.6-1) corrects for the
slight error due to the Class A/B operation of the output stage.
It can be estimated by subtracting the quiescent current in the
output stage from the total quiescent current and ratioing that
to the total quiescent current. For the AD8018,
α = 0.833.
+VS
–VS
+VO
+VS
–VS
–VO
RL
Figure 8. Simplified Differential Driver
Remembering that each output device dissipates for only half
the time gives a simple integral that computes the power for
each device:
1
2
∫
×
(
–
)
VV
V
R
SO
O
L
The total supply power can then be computed as:
PV
V
R
IV
P
TOT
S
O
L
Q
S
OUT
=
∫
∫
×+
+
4
1
2
||
α
In this differential driver, VO is the voltage at the output of one
amplifier, so 2 VO is the voltage across RL, which is the total
impedance seen by the differential driver, including back termina-
tion. Now, with two observations, the integrals are easily evaluated.
First, the integral of VO
2 is simply the square of the rms value of
VO. Second, the integral of |VO| is equal to the average recti-
fied value of VO, sometimes called the Mean Average Deviation, or
MAD. It can be shown that for a Discrete MultiTone (DMT)
signal, the MAD value is equal to 0.8 times the rms value.
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| AD8018ARZ-REEL7 | 功能描述:IC LINE DRIVER XDSL R-R 8SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:27 系列:- 類型:收發(fā)器 驅動器/接收器數:3/3 規(guī)程:RS232，RS485 電源電壓:4.75 V ~ 5.25 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
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