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參數(shù)資料
| 型號： | AD8044ANZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP VF R-R QUAD LP 14DIP |
| 標準包裝： | 25 |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 4 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 190 V/µs |
| -3db帶寬： | 160MHz |
| 電流 - 輸入偏壓： | 2µA |
| 電壓 - 輸入偏移： | 1400µV |
| 電流 - 電源： | 11.5mA |
| 電流 - 輸出 / 通道： | 30mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 12 V，±1.5 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-PDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 769 (CN2011-ZH PDF) |
AD8044
REV. B
–11–
Overdrive Recovery
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this over-
drive condition. As shown in Figure 33, the AD8044 recovers
within 50 ns from negative overdrive and within 25 ns from
positive overdrive.
50ns
1V
VS = +5V
AV = +2
RF = 2k
RL = 2k
VIN
2V/DIV
VOUT
1V/DIV
2V
Figure 33. Overdrive Recovery, VS + 5 V, VIN = 4 V Step
Circuit Description
The AD8044 is fabricated on Analog Devices’ proprietary
eXtra-Fast Complementary Bipolar (XFCB) process which
enables the construction of PNP and NPN transistors with
similar fTs in the 2 GHz–4 GHz region. The process is dielectri-
cally isolated to eliminate the parasitic and latch-up problems
caused by junction isolation. These features allow the construc-
tion of high frequency, low distortion amplifiers with low supply
currents. This design uses a differential output input stage to
maximize bandwidth and headroom (see Figure 34). The
smaller signal swings required on the first stage outputs (nodes
S1P, S1N) reduce the effect of nonlinear currents due to
junction capacitances and improve the distortion performance.
With this design harmonic distortion of better than –85 dB
@ 1 MHz into 100
W with VOUT = 2 V p-p (Gain = +2) on a
single 5 volt supply is achieved.
The AD8044’s rail-to-rail output range is provided by a comple-
mentary common-emitter output stage. High output drive capa-
bility is provided by injecting all output stage predriver currents
directly into the bases of the output devices Q8 and Q36. Bias-
ing of Q8 and Q36 is accomplished by I8 and I5, along with a
common-mode feedback loop (not shown). This circuit topol-
ogy allows the AD8044 to drive 50 mA of output current with
the outputs within 0.5 V of the supply rails.
On the input side, the device can handle voltages from –0.2 V
below the negative rail to within 1.2 V of the positive rail. Ex-
ceeding these values will not cause phase reversal; however, the
input ESD devices will begin to conduct if the input voltages
exceed the rails by greater than 0.5 V.
Driving Capacitance Loads
The capacitive load drive of the AD8044 can be increased by
adding a low valued resistor in series with the load. Figure 35
shows the effects of a series resistor on capacitive drive for vary-
ing voltage gains. As the closed-loop gain is increased, the larger
phase margin allows for larger capacitive loads with less over-
shoot. Adding a series resistor with lower closed-loop gains
accomplishes this same effect. For large capacitive loads, the
frequency response of the amplifier will be dominated by the
roll-off of the series resistor and capacitive load.
SIN
R21
R3
VEE
Q11
Q3
I10
R26
R39
Q5
Q4
Q40
I7
R2
R15
Q13
Q17
R5
C7
Q2
SIP
Q22
Q7
Q21
Q24
R23 R27
I2
I3
I1
Q51
Q25
Q50
Q39
Q47
Q27
Q31
Q23
I9
I5
VEE
VCC
I8
Q36
Q8
VOUT
C3
C9
VCC
VINP
VINN
VEE
I11
Figure 34. AD8044 Simplified Schematic
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