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參數(shù)資料
| 型號： | AD8044ARZ-14-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/17頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP VF R-R QUAD LP 14SOIC |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 4 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 190 V/µs |
| -3db帶寬： | 160MHz |
| 電流 - 輸入偏壓： | 2µA |
| 電壓 - 輸入偏移： | 1400µV |
| 電流 - 電源： | 11.5mA |
| 電流 - 輸出 / 通道： | 30mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 12 V，±1.5 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | AD8044ARZ-14REEL7 |
AD8044
REV. B
–13–
Active Filters
Active filters at higher frequencies require wider bandwidth op
amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly impact active filter
performance.
Figure 38 shows an example of a 2 MHz biquad bandwidth
filter that uses three op amps of an AD8044 package. Such
circuits are sometimes used in medical ultrasound systems to
lower the noise bandwidth of the analog signal before A/D
conversion.
2
3
1
R1
3k
VIN
R2
2k
C1
50pF
R3
2k
6
5
7
R6
1k
R5
2k
9
10
8
AD8044
C2
50pF
VOUT
R4
2k
Figure 38. 2 MHz Biquad Band-pass Filter Using AD8044
The frequency response of the circuit is shown in Figure 39.
FREQUENCY (Hz)
0
–10
10k
100M
100k
GAIN
(dB)
1M
10M
–20
–30
–40
Figure 39. Frequency Response of 2 MHz Band-pass
Biquad Filter
Layout Considerations
The specified high speed performance of the AD8044 requires
careful attention to board layout and component selection.
Proper RF design techniques and low-pass parasitic component
selection are necessary.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance path. The ground plane should be removed from the
area near the input pins to reduce the stray capacitance.
Chip capacitors should be used for the supply bypassing. One
end should be connected to the ground plane and the other
within 1/8 inch of each power pin. An additional large (0.47
mF
– 10
mF) tantalum electrolytic capacitor should be connected in
parallel, but not necessarily so close, to supply current for fast,
large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert-
ing input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50
W or 75 W and properly termi-
nated at each end.
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