參數(shù)資料
型號(hào)： AD8045ARDZ
廠商： ANALOG DEVICES INC
元件分類： 運(yùn)動(dòng)控制電子
英文描述： 3 nV/Hz Ultralow Distortion, High Speed Op Amp
中文描述： OP-AMP, 1000 uV OFFSET-MAX, PDSO8
封裝： MS-012, SOIC-8
文件頁(yè)數(shù)： 17/24頁(yè)
文件大小： 474K
代理商： AD8045ARDZ
AD8045
THEORY OF OPERATION
The AD8045 is a high speed voltage feedback amplifier fabri-
cated on ADI’s second generation eXtra Fast Complementary
Bipolar (XFCB) process. An H-bridge input stage is used to
attain a 1400 V/μs slew rate and low distortion in addition to a
low 3 nV/√Hz input voltage noise. Supply current and offset
voltage are laser trimmed for optimum performance.
Rev. A | Page 17 of 24
FREQUENCY RESPONSE
The AD8045’s open-loop response over frequency can be
approximated by the integrator response shown in Figure 63.
f
CROSSOVER
= 400MHz
FREQUENCY (MHz)
V
O
/
I
0
1
10
100
f
1000
V
OUT
/V
IN
=
f
CROSSOVER
V
IN
V
OUT
0
Figure 63. Open-Loop Response
The closed-loop transfer function for the noninverting configu-
ration is shown in Figure 64 and is written as
(
)
G
CROSSOVER
G
F
F
G
CROSSOVER
+
2
s
IN
OUT
V
R
f
R
R
R
R
f
V
×
×
+
+
×
×
=
π
)
(
π
2
where:
s
is (2 π
j
)
f
.
f
CROSSOVER
is the frequency where the amplifier’s open-loop gain
equals 1 (0 dB).
DC gain is therefore
(
)
G
F
G
IN
OUT
V
R
R
R
V
+
=
Closed-loop 3 dB bandwidth equals
(
)
F
G
G
+
CROSSOVER
IN
OUT
V
R
R
R
f
V
×
=
The closed-loop bandwidth is inversely proportional to the
noise gain of the op amp circuit, (R
F
+ R
G
)/R
G
. This simple
model can be used to predict the 3 dB bandwidth for noise
gains above +2. The actual bandwidth of circuits with noise
gains at or below +2 is higher due to the influence of other
poles present in the real op amp.
0
R
G
R
F
V
IN
V
OUT
R
S
+
–
Figure 64. Noninverting Configuration
DC ERRORS
Figure 65 shows the dc error contributions. The total output
error voltage is
+
+
+
+
=
+
G
F
G
OS
F
B
G
F
G
S
B
(ERROR)
OUT
V
R
R
R
V
R
I
R
R
R
R
I
0
R
G
R
F
V
OS
V
OUT
R
S
+
–
I
B
+
I
B
–
Figure 65. Amplifier DC Errors
The voltage error due to I
B
+ and I
B
is minimized if R
S
= R
F
||R
G
.
To include the effects of common-mode and power supply
rejection, model V
OS
as
CMR
V
PSR
V
V
V
CM
S
OS
OS
nom
+
+
=
where:
nom
os
V
is the offset voltage at nominal conditions.
Δ
V
S
is the change in the power supply voltage from nominal
conditions.
PSR
is the power supply rejection.
C
MR
is the common-mode rejection.
Δ
V
CM
is the change in common-mode voltage from nominal
conditions.
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