Data Sheet AD8057/AD8058 APPLICATIONS INFORMATION DRIVING CAPACITIVE LOADS When driving a capacitive lo" />
參數(shù)資料
型號: AD8057ARZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 5/16頁
文件大?。?/td> 0K
描述: IC OPAMP VF LN LP LDIST 8SOIC
標(biāo)準(zhǔn)包裝: 1,000
放大器類型: 電壓反饋
電路數(shù): 1
轉(zhuǎn)換速率: 1150 V/µs
-3db帶寬: 325MHz
電流 - 輸入偏壓: 500nA
電壓 - 輸入偏移: 1000µV
電流 - 電源: 6mA
電壓 - 電源,單路/雙路(±): 3 V ~ 12 V,±1.5 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 帶卷 (TR)
Data Sheet
AD8057/AD8058
APPLICATIONS INFORMATION
DRIVING CAPACITIVE LOADS
When driving a capacitive load, most op amps exhibit overshoot in
their pulse response. Figure 43 shows the relationship between
the capacitive load that results in 30% overshoot and the closed-
loop gain of an AD8058. It can be seen that, under the gain = +2
condition, the device is stable with capacitive loads of up to 69 pF.
In general, to minimize peaking or to ensure device stability for
larger values of capacitive loads, a small series resistor (RS) can
be added between the op amp output and the load capacitor
(CL) as shown in Figure 44.
For the setup shown in Figure 44, the relationship between RS
and CL was empirically derived and is shown in Table 4.
CLOSED-LOOP GAIN
500
400
0
5
1
2
3
4
C
L
(
pF)
300
200
100
RS = 2.4
RS = 0
01064-
044
Figure 43. Capacitive Load Drive vs. Closed-Loop Gain
–2.5V
RG
RF
RS
CL
VIN = 200mV p-p
AD8058
0.1F
10F
0.1F
10F
+2.5V
VOUT
FET PROBE
01064-
045
Figure 44. Capacitive Load Drive Circuit
Table 4. Recommended Value for Resistors RS, RF, RG vs.
Capacitive Load, CL, Which Results in 30% Overshoot
Gain
RF
RG
CL (RS = 0 )
CL (RS = 2.4 )
1
100
11 pF
13 pF
2
100
51 pF
69 pF
3
100
50
104 pF
153 pF
4
100
33.2
186 pF
270 pF
5
100
25
245 pF
500 pF
10
100
11
870 pF
1580 pF
50ns/DIV
100mV
–100mV
200mV
–200mV
+OVERSHOOT
29.0%
100mV/DIV
01064-
046
Figure 45. Typical Pulse Response with CL = 65 pF, Gain = +2, and VS = ±2.5
VIDEO FILTER
Some composite video signals that are derived from a digital
source contain some clock feedthrough that can cause problems
with downstream circuitry. This clock feedthrough is usually at
27 MHz, which is a standard clock frequency for both NTSC
and PAL video systems. A filter that passes the video band and
rejects frequencies at 27 MHz can be used to remove these fre-
quencies from the video signal.
Figure 46 shows a circuit that uses an AD8057 to create a single
5 V supply, 3-pole Sallen-Key filter. This circuit uses a single RC
pole in front of a standard 2-pole active section. To shift the dc
operating point to midsupply, ac coupling is provided by R4, R5,
and C4.
2
3
0.1F
+
10F
AD8057
7
4
6
+5V
R4
10k
R5
10k
C4
0.1F
R3
49.9
R2
499
C1
100pF
R1
200
RF
1k
C2
680pF
C3
36pF
01064-
047
Figure 46. Low-Pass Filter for Video
Rev. E | Page 13 of 16
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