AD8061/AD8062/AD8063
Data Sheet
Rev. J | Page 12 of 20
20ns/DIV
+0.1%
S
E
TTLIN
G
TIM
E
T
O
0.
1%
–0.1%
VS = 5V
RL = 1k
t = 0
1k
50
1k
RL = 1k
01065-
037
Figure 37. Output Settling Time to 0.1%
OUTPUT VOLTAGE STEP
50
0.5
S
E
TTLIN
G
TIM
E
(
ns
)
1.0
1.5
2.0
45
40
35
30
25
20
15
10
5
0
2.5
FALLING EDGE
RISING EDGE
VS = 5V
RL = 1k
G = +1
01065-
038
Figure 38. Settling Time vs. VOUT
2s
VS = 5V
G = –1
RF = 1k
RL = 1k
4.86V
2.43V
0V
1V
01065-
039
VO
L
TS
Figure 39. Output Swing
500mV/DIV
VS = 5V
G = +2
RL = 1k
VIN = 1V p-p
0
10
20
80
90
100
3.5V
TIME (ns)
2.5V
1.5V
70
60
50
40
30
01065-
040
V
OLTS
Figure 40. 1 V Step Response
20mV/DIV
VS = 5V
G = +2
RL = 1k
VIN = 100mV
0
10
20
80
90
100
2.6V
TIME (ns)
2.5V
2.4V
70
60
50
40
30
01065-
041
V
OLTS
Figure 41. 100 mV Step Response
2s/DIV
0V
1V/DIV
VS = 5V
G = +2
RF = RL = 1k
VIN = 4V p-p
01065-
042
V
OLTS
Figure 42. Output Rail-to-Rail Swing