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| 型號： | AD8073JRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO AMP TRIPLE 14-SOIC |
| 標準包裝： | 1,000 |
| 應(yīng)用： | 電流反饋 |
| 電路數(shù)： | 3 |
| -3db帶寬： | 100MHz |
| 轉(zhuǎn)換速率： | 500 V/µs |
| 電流 - 電源： | 3.5mA |
| 電流 - 輸出 / 通道： | 30mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 12 V，±2.5 V ~ 6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOICN |
| 包裝： | 帶卷 (TR) |
REV. D
AD8072/AD8073
–10–
Crosstalk
Crosstalk between internal amplifiers may vary depending on
which amplifier is being driven and how many amplifiers are
being driven. This variation typically stems from pin location on
the package and the internal layout of the IC itself. Table I
illustrates the typical crosstalk results for a combination of
conditions.
Table I. AD8073JR Crosstalk Table (dB)
Receive Amplifier
AD8073JR
12
3
1
X
–60
–56
Drive
2
–60
X
–60
Amplifier
3
–54
–60
X
All Hostile
–53
–55
–54
CONDITIONS
VS =
±5 V
RF = 1 k
, R
L = 150
AV = 2
VOUT = 2 V p-p on Drive Amplifier
Layout Considerations
The specified high speed performance of the AD8072 and
AD8073 require careful attention to board layout and compo-
nent selection. Proper RF design techniques and low parasitic
component selection are mandatory.
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
ground path. The ground plane should be removed from the
area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing. One end
of the capacitor should be connected to the ground plane and
the other within 1/8 inches of each power pin. An additional
large (4.7
F–10 F) tantalum electrolytic capacitor should be
connected in parallel, but not necessarily as close to the supply
pins, to provide current for fast large-signal changes at the
device’s output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert-
ing input will affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than approximately 1 inch). These should be designed
with a characteristic impedance of 50
or 75 and be properly
terminated at each end.
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