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參數資料
| 型號： | AD8074ARUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 15/15頁 |
| 文件大小： | 0K |
| 描述： | IC TRPL VID BUFF 500MHZ 16-TSSOP |
| 標準包裝： | 1,000 |
| 應用： | 緩沖器 |
| 電路數： | 3 |
| -3db帶寬： | 600MHz |
| 轉換速率： | 1600 V/µs |
| 電流 - 電源： | 21.5mA |
| 電流 - 輸出 / 通道： | 70mA |
| 電壓 - 電源，單路/雙路(±)： | 9 V ~ 11 V，±4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
AD8074/AD8075
–9–
THEORY OF OPERATION
The AD8074 (G = +1) and AD8075 (G = +2) are triple-channel,
high-speed buffers with TTL-compatible output enable control.
Optimized for buffering RGB (red, green, blue) video sources,
the devices have high peak slew rates, maintaining their band-
width for large signals. Additionally, the buffers are compensated
for high phase margin, minimizing overshoot for good pixel
resolution. The buffers also have video specifications that are
suitable for buffering NTSC or PAL composite signals.
The buffers are organized as three independent channels, each
with an input transconductance stage and an output trans-
impedance stage. Each channel is characterized by low input
capacitance and high input impedance. The transconductance
stages, NPN differential pairs, source signal current into the folded
cascode output stages. Each output stage contains a compensat-
ing network and emitter follower output buffer. Internal voltage
feedback sets the gain, the AD8074 being configured as a unity
gain follower, and the AD8075 as a gain-of-two amplifier with a
feedback network. The architecture provides drive for a reverse-
terminated video load (150
) with low differential gain and
phase error for relatively low power consumption. Careful chip
design and layout allow excellent crosstalk isolation between
channels.
One logic pin,
OE, controls whether the three outputs are
enabled, or disabled to a high-impedance state. The high imped-
ance disable allows larger matrices to be built when busing the
outputs together. When disabled, the AD8074 and AD8075 con-
sume a fifth the power as when enabled. In the case of the
AD8075 (G = +2), a feedback isolation scheme is used so that
the impedance of the gain-of-two feedback network does not
load the output.
Full power bandwidth for an undistorted sinusoid is often calcu-
lated using peak slew rate from the equation:
Full Power Bandwidth
Peak Slew Rate
Sinusoidal Amplitude
=
××
2
π
Peak slew rate is not the same as average slew rate (25% to
75%) which is typically specified. For a natural response, peak
slew rate may be 2.7 times larger than average slew rate. There-
fore, calculating a full power bandwidth with a specified average
slew rate will give a pessimistic result.
The primary cause of overshoot in these amplifiers is the pres-
ence of large reactive loads at the output and insufficient series
isolation of the load. However, it is possible to overdrive these
amplifiers with 1 V, subnanosecond input-pulse edges. The
ensuing dynamics may give rise to subnanosecond overshoot. To
reduce these effects, an edge-rate limiting network at the input
should be considered for input transition times less than 0.5 ns.
APPLICATIONS
Response Tuning
It has been mentioned in passing that the primary cause of over-
shoot for the AD8074 and AD8075 is the presence of large
reactive loads at the output. If the system exhibits excessive
ringing while settling, a 10
–50 series resistor may be used
at the output to isolate the emitter-follower output buffer from
the reactive load. If the output exhibits an overdamped response,
the system designer may add a few pF shunt capacitance at the
output to tune for a faster edge transition. A system with a small
degree of overshoot will settle faster than an overdamped system.
VIN
VOUT
RS
CL
1k
75
2ns
RS = 0
CL = 5pF
RS = 10
CL = 10pF
RS = 20
CL = 15pF
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
Figure 2. Driving Capacitive Loads
Single Supply Operation
The AD8074 and AD8075 may be operated from a single 10 V
supply. In this configuration, the AD8075’s AGND pins must
be tied near midsupply, as AGND provides the reference for the
ground buffer, to which the internal gain network is terminated.
Logic is referenced to DGND. The buffers are disabled in single
supply operation for VOE > VDGND + ~2.0 V and enabled for
VOE < VDGND + 0.8 V. TTL logic levels are expected. The fol-
lowing restrictions are placed upon the digital ground potential:
35
12
.
–
VV
V
AVCC
DGND
≤≤
VDGND
≥ VAVEE
The architecture of the output buffer is such that the output
voltage can swing to within ~2.3 V of either rail. For example, if
the output need swing only 2 V, then the buffers could be oper-
ated on dual 3.5 V or single 7 V supplies. It is cautioned that
saturation effects may become noticeable when the output swings
within 2.6 V of either rail. The system designer may opt to
use this characteristic to his or her advantage by using the
soft-saturation regime, (2.2 V–2.6 V from the supply rails), to
tame excessive overshoot. The designer is cautioned that a
charge storage associated time delay of several nanoseconds is
incurred when recovering from soft-saturation. This effect
results in longer settling tails.
Rev. B
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