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| 型號： | AD808-622BRZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 0K |
| 描述： | IC RECEIVER FIBER OPTIC 16SOIC |
| 標準包裝： | 1,000 |
| 類型： | 接收器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a FiberOpticReceiverwithQuantizerand
Clock Recovery and Data Retiming
AD808
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
FEATURES
Meets CCITT G.958 Requirements
for STM-4 Regenerator—Type A
Meets Bellcore TR-NWT-000253 Requirements for OC-12
Output Jitter: 2.5 Degrees RMS
622 Mbps Clock Recovery and Data Retiming
Accepts NRZ Data, No Preamble Required
Phase-Locked Loop Type Clock Recovery—
No Crystal Required
Quantizer Sensitivity: 4 mV
Level Detect Range: 10 mV to 40 mV, Programmable
Single Supply Operation: +5 V or –5.2 V
Low Power: 400 mW
10 KH ECL/PECL Compatible Output
Package: 16-Lead Narrow 150 mil SOIC
frequency acquisition without false lock. This eliminates a reli-
ance on external components such as a crystal or a SAW filter,
to aid frequency acquisition.
The AD808 acquires frequency and phase lock on input data
using two control loops that work without requiring external
control. The frequency acquisition control loop initially acquires
the frequency of the input data, acquiring frequency lock on
random or scrambled data without the need for a preamble. At
frequency lock, the frequency error is zero and the frequency
detector has no further effect. The phase acquisition control
loop then works to ensure that the output phase tracks the input
phase. A patented phase detector has virtually eliminated pat-
tern jitter throughout the AD808.
The device VCO uses a ring oscillator architecture and patented
low noise design techniques. Jitter is 2.5 degrees rms. This low
jitter results from using a fully differential signal architecture,
Power Supply Rejection Ratio circuitry and a dielectrically
isolated process that provides immunity from extraneous signals
on the IC. The device can withstand hundreds of millivolts of
power supply noise without an effect on jitter performance.
The user sets the jitter peaking and acquisition time of the PLL
by choosing a damping factor capacitor whose value determines
loop damping. CCITT G.958 Type A jitter transfer require-
ments can easily be met with a damping factor of 5 or greater.
Device design guarantees that the clock output frequency will
drift by less than 20% in the absence of input data transitions.
Shorting the damping factor capacitor, CD, brings the clock
output frequency to the VCO center frequency.
The AD808 consumes 400 mW and operates from a single
power supply at either +5 V or –5.2 V.
FUNCTIONAL BLOCK DIAGRAM
SIGNAL
LEVEL
DETECTOR
COMPENSATING
ZERO
VCO
RETIMING
DEVICE
LOOP
FILTER
DET
PIN
NIN
THRADJ
SDOUT
CLKOUTP
CLKOUTN
DATAOUTP
DATAOUTN
LEVEL
DETECT
COMPARATOR/
BUFFER
AD808
PHASE-LOCKED LOOP
CF1
CF2
QUANTIZER
FDET
PRODUCT DESCRIPTION
The AD808 provides the receiver functions of data quantiza-
tion, signal level detect, clock recovery and data retiming for
622 Mbps NRZ data. The device, together with a PIN
diode/preamplifier combination, can be used for a highly inte-
grated, low cost, low power SONET OC-12 or SDH STM-4
fiber optic receiver.
The receiver front end signal level detect circuit indicates when
the input signal level has fallen below a user adjustable thresh-
old. The threshold is set with a single external resistor. The
signal level detect circuit 3 dB optical hysteresis prevents chatter
at the signal level detect output.
The PLL has a factory trimmed VCO center frequency and a
frequency acquisition control loop that combine to guarantee
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