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參數(shù)資料
| 型號： | AD8092ARM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | Low-Cost, High-Speed Rail-to-Rail Amplifiers |
| 中文描述： | DUAL OP-AMP, 27000 uV OFFSET-MAX, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 229K |
| 代理商： | AD8092ARM |
–5–
AD8091/AD8092
REV. A
ABSOLUTE MAXIMUM RATINGS
*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . .
±
V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . .
±
2.5 V
Output Short Circuit Duration . . . . . . . . . . . . . See Figure 1
Storage Temperature Range . . . . . . . . . . .
–
65
°
C to +125
°
C
Operating Temperature Range . . . . . . . . . . .
–
40
°
C to +85
°
C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300
°
C
*
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this speci
fi
cation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8091/AD8092
package is limited by the associated rise in junction temperature
(T
J
) on the die. The plastic encapsulating the die will locally reach
the junction temperature. At approximately 150
°
C, which is the
glass transition temperature, the plastic will change its properties.
Even temporarily exceeding this temperature limit may change the
stresses that the package exerts on the die, permanently shifting the
parametric performance of the AD8091/AD8092. Exceeding a
junction temperature of 175
°
C for an extended period of time can
result in changes in the silicon devices, potentially causing failure.
The still-air thermal properties of the package (
JA
), ambient
temperature (T
A
), and the total power dissipated in the package
(P
D
) can be used to determine the junction temperature of the die.
The junction temperature can be calculated as follows:
T
T
P
A
D
A
J
J
=
+
×
(
)
θ
The power dissipated in the package (P
D
) is the sum of the quies-
cent power dissipation and the power dissipated in the package
due to the load drive for all outputs. The quiescent power is the
voltage between the supply pins (V
S
) times the quiescent current
(I
S
). Assuming the load (R
L
) is referenced to midsupply, then the
total drive power is V
S
/2 I
OUT
, some of which is dissipated in
the package and some in the load (V
OUT
I
OUT
). The difference
between the total drive power and the load power is the drive
power dissipated in the package.
P
D
= quiescent power + (total drive power – load power)
P
V
(
I
V
V
R
V
R
S
S
S
OUT
L
OUT
L
D
=
×
)
+
×
2
2
–
RMS output voltages should be considered. (If R
L
is referenced
to V
S
–
, as in single-supply operation, then the total drive power is
V
S
I
OUT
.)
If the rms signal levels are indeterminate, then consider the
worst case, when V
OUT
= V
S
/4 for R
L
to midsupply:
P
V
(
I
V
R
D
S
S
S
L
=
×
)
+
4
2
(In single-supply operation with R
L
referenced to V
S
–
, worst case is
V
OUT
= V
S
/2.)
Airflow will increase heat dissipation, effectively reducing
JA
. Also,
more metal directly in contact with the package leads from metal
traces, through holes, ground, and power planes will reduce the
JA
.
Care must be taken to minimize parasitic capacitances at the input
leads of high-speed op amps as discussed in the board layout
section.
Figure 1 shows the maximum safe power dissipation in the package
versus the ambient temperature for the SOIC-8 (125
°
C/W),
SOT23-5 (180
°
C/W), and
μ
SOIC-8 (150
°
C/W) packages on a
JEDEC standard four-layer board.
AMBIENT TEMPERATURE
–
C
2.0
1.0
0
–
40
M
–
–
30
1.5
0.5
80
40
50
10
–
10
30
T
J
= 150 C
SOIC-8
SOIC-8
–
20
0
20
60
70
90
SOT23-5
Figure 1. Maximum Power Dissipation vs. Temperature
for a Four-Layer Board
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