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    • 參數(shù)資料
      型號(hào): AD8099ARD-REEL7
      廠商: Analog Devices Inc
      文件頁數(shù): 26/29頁
      文件大?。?/td> 0K
      描述: IC OPAMP VF ULN ULDIST 8SOIC
      產(chǎn)品培訓(xùn)模塊: Practical Guide High Speed PCB Layout
      標(biāo)準(zhǔn)包裝: 1,000
      放大器類型: 電壓反饋
      電路數(shù): 1
      轉(zhuǎn)換速率: 1350 V/µs
      -3db帶寬: 510MHz
      電流 - 輸入偏壓: 6µA
      電壓 - 輸入偏移: 100µV
      電流 - 電源: 15mA
      電流 - 輸出 / 通道: 178mA
      電壓 - 電源,單路/雙路(±): 5 V ~ 12 V,±2.5 V ~ 6 V
      工作溫度: -40°C ~ 125°C
      安裝類型: 表面貼裝
      封裝/外殼: 8-SOIC(0.154",3.90mm Width)裸露焊盤
      供應(yīng)商設(shè)備封裝: 8-SOIC-EP
      包裝: 帶卷 (TR)
      Data Sheet
      AD8099
      Rev. D | Page 5 of 28
      ABSOLUTE MAXIMUM RATINGS
      Table 3.
      Parameter
      Rating
      Supply Voltage
      12.6 V
      Power Dissipation
      Differential Input Voltage
      ±
      1.8 V
      Differential Input Current
      ±10mA
      Storage Temperature
      –65°C to +125°C
      Operating Temperature Range
      –40°C to +125°C
      Lead Temperature Range (Soldering 10 sec)
      300°C
      Junction Temperature
      150°C
      Stresses above those listed under Absolute Maximum Ratings
      may cause permanent damage to the device. This is a stress
      rating only; functional operation of the device at these or any
      other conditions above those indicated in the operational
      section of this specification is not implied. Exposure to absolute
      maximum rating conditions for extended periods may affect
      device reliability.
      MAXIMUM POWER DISSIPATION
      The maximum safe power dissipation in the AD8099 package is
      limited by the associated rise in junction temperature (TJ) on
      the die. The plastic encapsulating the die will locally reach the
      junction temperature. At approximately 150°C, which is the
      glass transition temperature, the plastic will change its
      properties. Even temporarily exceeding this temperature limit
      may change the stresses that the package exerts on the die,
      permanently shifting the parametric performance of the
      AD8099. Exceeding a junction temperature of 150°C for an
      extended period can result in changes in silicon devices,
      potentially causing failure.
      The still-air thermal properties of the package and PCB (θJA),
      the ambient temperature (TA), and the total power dissipated in
      the package (PD) determine the junction temperature of the die.
      The junction temperature can be calculated as
      (
      )
      JA
      D
      A
      J
      θ
      P
      T
      ×
      +
      =
      The power dissipated in the package (PD) is the sum of the
      quiescent power dissipation and the power dissipated in the
      package due to the load drive for all outputs. The quiescent
      power is the voltage between the supply pins (VS) times the
      quiescent current (IS). Assuming the load (RL) is referenced to
      midsupply, the total drive power is VS/2 × IOUT, some of which is
      dissipated in the package and some in the load (VOUT × IOUT).
      The difference between the total drive power and the load
      power is the drive power dissipated in the package.
      PD = Quiescent Power + (Total Drive Power – Load Power)
      (
      )
      L
      2
      OUT
      L
      OUT
      S
      D
      R
      V
      R
      V
      2
      V
      I
      V
      P
      ×
      +
      ×
      =
      RMS output voltages should be considered. If RL is referenced to
      VS–, as in single-supply operation, then the total drive power is
      VS × IOUT. If the rms signal levels are indeterminate, consider the
      worst case, when VOUT = VS/4 for RL to midsupply:
      (
      ) (
      )
      L
      S
      D
      R
      /
      V
      I
      V
      P
      2
      4
      +
      ×
      =
      In single-supply operation with RL referenced to VS–, worst case
      is VOUT = VS/2.
      Airflow will increase heat dissipation, effectively reducing θJA.
      Also, more metal directly in contact with the package leads
      from metal traces, through holes, ground, and power planes will
      reduce the θJA. Soldering the exposed paddle to the ground
      plane significantly reduces the overall thermal resistance of the
      package. Care must be taken to minimize parasitic capaci-
      tances at the input leads of high speed op amps, as discussed in
      Figure 4 shows the maximum safe power dissipation in the
      package versus the ambient temperature for the exposed paddle
      (e-pad) SOIC-8 (70°C/W), and LFCSP (70°C/W), packages on a
      JEDEC standard 4-layer board. θJA values are approximations.
      04511-0-115
      AMBIENT TEMPERATURE (°C)
      120
      –40
      –20
      0
      20
      40
      60
      80
      100
      MAXIMUM
      POWER
      DISSIPATION
      (Watts)
      0.0
      4.0
      3.5
      3.0
      2.5
      2.0
      1.5
      1.0
      0.5
      LFCSP AND SOIC
      Figure 4. Maximum Power Dissipation
      ESD CAUTION
      ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
      the human body and test equipment and can discharge without detection. Although this product features
      proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
      electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
      degradation or loss of functionality.
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