參數(shù)資料
型號(hào)： AD8099ARD
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/29頁(yè)
文件大?。?/td> 0K
描述： IC OPAMP VF ULN ULDIST 8SOIC
產(chǎn)品培訓(xùn)模塊： Practical Guide High Speed PCB Layout
標(biāo)準(zhǔn)包裝： 98
放大器類型： 電壓反饋
電路數(shù)： 1
轉(zhuǎn)換速率： 1350 V/µs
-3db帶寬： 510MHz
電流 - 輸入偏壓： 6µA
電壓 - 輸入偏移： 100µV
電流 - 電源： 15mA
電流 - 輸出 / 通道： 178mA
電壓 - 電源，單路/雙路(±)： 5 V ~ 12 V，±2.5 V ~ 6 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm Width）裸露焊盤
供應(yīng)商設(shè)備封裝： 8-SOIC-EP
包裝： 管件
Data Sheet
AD8099
Rev. D | Page 23 of 28
CIRCUIT CONSIDERATIONS
Optimizing the performance of the AD8099 requires attention
to detail in layout and signal routing of the board. Power supply
bypassing, parasitic capacitance, and component selection all
contribute to the overall performance of the amplifier. The
AD8099 features an exposed paddle on the backs of both the
LFCSP and SOIC packages. The exposed paddle provides a low
thermal resistive path to the ground plane. For best
performance, solder the exposed paddle to the ground plane.
PCB Layout
The compensation network is determined by the amplifier gain
requirements. For lower gains, the layout and component
placement are more critical. For higher gains, there are fewer
compensation components, which results in a less complex
layout. With diligent consideration to layout, grounding, and
component placement, the AD8099 evaluation boards have
been optimized for peak performance. These are the same
evaluation boards that are available to customers; see the
Ordering Guide for ordering information.
Parasitics
The area surrounding the compensation pin is very sensitive to
parasitic capacitance. To realize the full gain bandwidth product
of the AD8099, there should be no trace connected to or within
close proximity of the external compensation pin for the lowest
possible capacitance. When compensation is required, the
traces to the compensation pin, the negative supply, and the
interconnect between components (i.e. CC, C1, and RC in
Figure 59) should be made as wide as possible to minimize
inductance.
All ground and power planes under the pins of the AD8099
should be cleared of copper to prevent parasitic capacitance
between the input and output pins to ground. A single mount-
ing pad on a SOIC footprint can add as much as 0.2 pF of
capacitance to ground as a result of not clearing the ground or
power plane under the AD8099 pins. Parasitic capacitance can
cause peaking and instability, and should be minimized to
ensure proper operation.
The new pinout of the AD8099 reduces the distance between
the output and the inverting input of the amplifier. This helps to
minimize the parasitic inductance and capacitance of the
feedback path, which, in turn, reduces ringing and second
harmonic distortion.
Grounding
When possible, ground and power planes should be used.
Ground and power planes reduce the resistance and inductance
of the power supply feeds and ground returns. If multiple planes
are used, they should be “stitched” together with multiple vias.
The returns for the input, output terminations, bypass
capacitors, and RG should all be kept as close to the AD8099 as
possible. Ground vias should be placed at the very end of the
component mounting pad to provide a solid ground return. The
output load ground and the bypass capacitor grounds should be
returned to a common point on the ground plane to minimize
parasitic inductance and improve distortion performance. The
AD8099 packages feature an exposed paddle. For optimum
performance, solder this paddle to ground. For more infor-
mation on PCB layout and design considerations, refer to
section 7-2 of the 2002 Analog Devices Op Amp Applications
book.
Power Supply Bypassing
The AD8099 power supply bypassing has been optimized for
each gain configuration as shown in Figure 60 through
Figure 66 in the Circuit Configurations section. The values
shown should be used when possible. Bypassing is critical for
stability, frequency response, distortion, and PSRR
performance. The 0.1 F capacitors shown in Figure 60 through
Figure 66 should be as close to the supply pins of the AD8099 as
possible and the electrolytic capacitors beside them.
Component Selection
Smaller components less than 1206 SMT case size, offer smaller
mounting pads, which have less parasitics and allow for a more
compact layout. It is critical for optimum performance that high
quality, tight tolerance (where critical), and low drift compo-
nents be used. For example, tight tolerance and low drift is
critical in the selection of the feedback capacitor used in
Figure 60. The feedback compensation capacitor in Figure 60 is
1.5pF. This capacitor should be specified with NPO material.
NPO material typically has a ±30 ppm/°C change over –55°C to
+125°C temperature range. For a 100°C change, this would
result in a 4.5 fF change in capacitance, compared to an X7R
material, which would result in a 0.23 pF change, a 15% change
from the nominal value. This could introduce excessive
peaking, as shown in Figure 68, CF vs. Frequency Response.
DESIGN TOOLS AND TECHNICAL SUPPORT
Analog Devices is committed to the design process by providing
technical support and online design tools. ADI offers technical
support via evaluation boards, sample ICs, SPICE models,
interactive evaluation tools, application notes, phone and email
support—all available at www.analog.com.
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