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| 型號： | AD8099ARDZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/29頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP VF ULN ULDIST 8SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Practical Guide High Speed PCB Layout |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 1350 V/µs |
| -3db帶寬： | 510MHz |
| 電流 - 輸入偏壓： | 6µA |
| 電壓 - 輸入偏移： | 100µV |
| 電流 - 電源： | 15mA |
| 電流 - 輸出 / 通道： | 178mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 12 V，±2.5 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm Width）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC-EP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD8099
Rev. D | Page 21 of 28
04511-0-070
GAIN FROM
"B" TO OUTPUT
=–
R2
R1
GAIN FROM
"A" TO OUTPUT
=
NOISE GAIN =
NG = 1 +
R2
R1
IN–
VN
VN, R1
VN, R3
R1
R2
IN+
R3
4kTR2
4kTR1
4kTR3
VN, R2
B
A
VN2 + 4kTR3 + 4kTR1
R2
2
R1 + R2
IN+2R32 + IN–2
R1 × R2
2
+ 4kTR2
R1
2
R1 + R2
RTI NOISE =
RTO NOISE = NG × RTI NOISE
VOUT
+
Figure 69. Op Amp Noise Analysis Model
In applications where noise sensitivity is critical, care must be
taken not to introduce other significant noise sources to the
amplifier. Each resistor is a noise source. Attention to the
following areas is critical to maintain low noise performance:
design, layout, and component selection. A summary of noise
performance for the amplifier and associated resistors can be
seen in Table 4.
INPUT BIAS CURRENT AND DC OFFSET
In high noise gain configurations, the effects of output offset
voltage can be significant, even with low input bias currents and
input offset voltages. Figure 70 shows a comprehensive offset
voltage model, which can be used to determine the referred to
output (RTO) offset voltage of the amplifier or referred to input
(RTI) offset voltage.
04511-0-071
GAIN FROM
"B" TO OUTPUT
=–
R2
R1
GAIN FROM
"A" TO OUTPUT
=
NOISE GAIN =
NG = 1 +
R2
R1
IB–
VOS
R1
R2
IB+
R3
B
A
OFFSET (RTO) = VOS 1 +
R2
+ IB+ × R3 1 +
R2
– IB– × R2
R1
OFFSET (RTI) = VOS + IB+ × R3 – IB–
R1 × R2
R1 + R2
OFFSET (RTI) = VOS
IF IB+ = IB– AND R3 =
R1 × R2
R1 + R2
VOUT
FOR BIAS CURRENT CANCELLATION:
Figure 70. Op Amp Total Offset Voltage Model
For RTO calculations, the input offset voltage and the voltage
generated by the bias current flowing through R3 are multiplied
by the noise gain of the amplifier. The voltage generated by IB–
through R2 is summed together with the previous offset
voltages to arrive at a final output offset voltage. The offset
voltage can also be referred to the input (RTI) by dividing the
calculated output offset voltage by the noise gain.
parallel combination of R1 and R2, then the RTI offset voltage
can be reduced to only VOS. This is a common method used to
reduce output offset voltage. Keeping resistances low helps to
minimize offset error voltage and keeps the voltage noise low.
DISABLE PIN AND INPUT BIAS CANCELLATION
The AD8099 DISABLE pin performs three functions; enable,
disable, and reduction of the input bias current. When the
DISABLE pin is brought to within 0.7 V of the positive supply,
the input bias current is reduced by an approximate factor of 60.
However, the input current noise doubles to 5.2 pA/Hz.
Table 5 outlines the DISABLE pin functionality.
Table 5. DISABLE Pin Truth Table
Supply Voltage
±5 V
+5 V
Disable
–5 to +2.4
0 to 2.4
Enable
Open
Low Input Bias Current
4.3 to 5
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| AD8099ARDZ-REEL7 | 功能描述:IC OPAMP VF ULN ULDIST 8SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:50 系列:LinCMOS™ 放大器類型:通用 電路數(shù):4 輸出類型:- 轉(zhuǎn)換速率:0.05 V/µs 增益帶寬積:110kHz -3db帶寬:- 電流 - 輸入偏壓:0.7pA 電壓 - 輸入偏移:210µV 電流 - 電源:57µA 電流 - 輸出 / 通道:30mA 電壓 - 電源，單路/雙路(±):3 V ~ 16 V，±1.5 V ~ 8 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:管件 產(chǎn)品目錄頁面:865 (CN2011-ZH PDF) 其它名稱:296-1834296-1834-5 |
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