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參數(shù)資料
| 型號(hào)： | AD8104ABPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 29/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWIT 32X16 304BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 交叉點(diǎn)開(kāi)關(guān) |
| 電路： | 1 x 32:16 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V，±2.5V |
| 電流 - 電源： | 340mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 304-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 304-BGA（31x31） |
| 包裝： | 托盤 |
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AD8104/AD8105
Rev. 0 | Page 35 of 36
If multiple AD8104/AD8105s are to be driven in parallel, a fly-
by input termination scheme is very useful, but the distance
from each AD8104/AD8105 input to the driven input transmis-
sion line is a stub that should be minimized in length and
parasitics using the discussed guidelines.
When driving the AD8104/AD8105 single-endedly, the
undriven input is often terminated with a resistance to balance
the input stage. It can be seen that by terminating the undriven
input with a resistor of one half the characteristic impedance,
the input stage is perfectly balanced (37.5 Ω, for example, to
balance the two parallel 75 Ω terminations on the driven input).
However, due to the feedback in the input receiver, there is high
speed signal current leaving the undriven input. To terminate
this high speed signal, proper transmission line techniques
should be used. One solution is to adjust the trace width to
create a transmission line of half the characteristic impedance
and terminate the far end with this resistance (37.5 Ω in a 75 Ω
system). This is not often practical as trace widths become large.
In most cases, the best practical solution is to place the half-
characteristic impedance resistor as close as possible (preferably
less than 1.5 cm away) and to reduce the parasitics of the stub
(by removing the ground plane under the stub, for example).
In either case, the designer must decide if the layout complexity
created by a balanced, terminated solution is preferable to
simply grounding the undriven input at the ball with no trace.
Although the examples discussed so far are for input termina-
tion, the theory is similar for output back-termination. Taking
the AD8104/AD8105 as an ideal voltage source, any distance of
routing between the AD8104/AD8105 and a back-termination
resistor will be an impedance mismatch that potentially creates
reflections. For this reason, back-termination resistors should
also be placed close to the AD8104/AD8105. In practice,
because back-termination resistors are series elements, they
can be placed close to the AD8104/AD8105 outputs.
GND
VOCM
VDD
AD8104/
AD8105
ON[15:0], OP[15:0]
IN[31:0], IP[31:0]
CLK
RESET
WE
UPDATE
DATA IN
DATA OUT
J3
PLD_VDD
PC_VDD
PC_GND
SMA
VPOS
VNEG
DGND
VDD
VPOS
VNEG
CPLD
50
LOGIC
PC
PARALLEL
PORT
IN[31:0],
IP[31:0]
LOGIC
ISOLATORS
J8,
W3 TO W7
D0 TO D5
A0 TO A3
ON[15:0],
OP[15:0]
ANALOG
06
61
2-
0
73
Figure 73. Evaluation Board Simplified Schematic
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