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參數(shù)資料
| 型號： | AD8123ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RCVR TRPL DIFF EQUAL 40LFCSP |
| 標準包裝： | 2,500 |
| 類型： | 接收器 |
| 驅(qū)動器/接收器數(shù)： | 0/3 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
AD8123
Rev. A | Page 13 of 16
USING THE AD8123 WITH COAXIAL CABLE
The VPOLE control allows the AD8123 to be used with other
types of cable, including coaxial cable. Figure 18 presents the
recommended settings for VPEAK, VPOLE, and VGAIN when the
AD8123 is used with good quality 75 Ω video cable. Figure 24
shows how to derive VPOLE and VGAIN from VPEAK in a coaxial
cable application where VPEAK originates from a low-Z source.
20
5.11k
20k
VPEAK
–5V
+5V
24.3k
47.5k
1.16k
VGAIN ≈ 1.06 × VPEAK – 0.62V
VPOLE ≈ 0.76 × VPEAK – 0.41V
10k
1.24k
0
681
4-
0
29
Figure 24. Deriving VPOLE and VGAIN from VPEAK with Low-Z Source for Coaxial Cable
The op amp in the circuit that develops VGAIN is required to
insert the offset of 0.62 V with a gain from VPEAK to VGAIN that
is close to unity. A passive offset circuit would require an offset
injection voltage that is much larger in magnitude than the
available 5 V supply. Clearly, the VGAIN control voltage can
also be developed independently.
The AD8123 differential input can accept signals carried over
unbalanced cable, as shown in Figure 25, for an unbalanced
75 Ω coaxial cable termination.
75
06
81
4-
03
0
INPUT FROM
75 CABLE
AD8123
INPUT STAGE
Figure 25. Terminating a 75 Ω Cable
DRIVING 75 Ω VIDEO CABLE WITH THE AD8123
When the RGB outputs must drive a 75 Ω line rather than a
high impedance load, an additional gain of two is required to
make up for the double termination loss (75 Ω source and load
terminations). There are two options available for this.
One option is to place the additional gain of 2 at the drive end
by using the AD8148 triple differential driver to drive the cable.
The AD8148 has a fixed gain of 4 instead of the usual gain of 2
and thereby provides the required additional gain of 2 without
having to add additional amplifiers to the signal chain. The
AD8148 also contains sync-on-common-mode encoding. If
sync-on-common-mode is not required, it can be deactivated
on the AD8148 by connecting its SYNC LEVEL input to ground.
The other option is to include a triple gain-of-2 buffer, such as the
ADA4862-3, on the AD8123 RGB outputs, as shown in Figure 26
for one channel (power supplies not shown). The ADA4862-3
provides the gain of 2 that compensates for the double-
termination loss.
06
81
4-
0
22
ONE VIDEO
OUTPUT
FROM AD8123
ONE CHANNEL OF ADA4862-3
75
75
500
Z0 = 75
Figure 26. Using ADA4862-3 on AD8123 Outputs
DRIVING A CAPACITIVE LOAD
When driving a high impedance capacitive input, it is necessary
to place a small series resistor between each of the three AD8123
video outputs and the load to buffer the input capacitance of the
device being driven. Clearly, the resistor value must be small
enough to preserve the required bandwidth.
FILTERING THE RGB OUTPUTS
In some cases, it is desirable to place low-pass filters on the
AD8123 video outputs to reduce high frequency noise. A 3-pole
Butterworth filter with cutoff frequency in the neighborhood of
present filters for the high impedance load case (driving a delay
line, crosspoint switch, ADA4862-3) and the double-termination
case (75 Ω source and load resistances), respectively. In the high
impedance load case, the load capacitance must be absorbed in
the capacitor that is placed across the load. For example, in
Figure 27, if the high-Z load were the input to an ADA4862-3,
which has an input capacitance of 2 pF, the filter capacitor value
in parallel with the input would be 15 pF to obtain 17 pF.
06
81
4-
0
23
*INPUT CAPACITANCE OF LOAD MUST BE
ABSORBED INTO THIS VALUE.
HIGH-Z
150nH
100
5.6pF
17pF*
AD8123
OUTPUT
Figure 27. 140 MHz Low-Pass Filter on AD8123 Output Feeding High-Z Load
06
81
4-
02
4
180nH
75
75
Z0 = 75
15pF
AD8123
OUTPUT
Figure 28. 135 MHz Low-Pass Filter on AD8123 Output Feeding
Doubly Terminated Load
These filters are by no means the only choices but are presented
here as examples. In the high-Z load case, it is important to
keep the filter source resistance large enough to buffer the
capacitive loading presented by the first capacitor in the filter.
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| AD8123ACPZ-RL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Triple Differential Receiver with Adjustable Line Equalization |
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| AD8124ACPZ | 功能描述:IC HS RCVR EQUALIZER 40VFQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD8124ACPZ-R7 | 功能描述:IC RCVR TRPL DIFF EQUAL 40LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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