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參數(shù)資料
| 型號： | AD8138AR-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Distortion Differential ADC Driver |
| 中文描述： | LINE DRIVER, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 231K |
| 代理商： | AD8138AR-REEL7 |
AD8138
–9–
REV. A
OPERATIONAL DESCRIPTION
Definition of Terms
AD8138
CF
+IN
–IN
RF
CF
RF
RG
+DIN
VOCM
–DIN
RL,dm
+OUT
VOUT,dm
–OUT
Figure 36. Circuit Definitions
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or
equivalently output differential-mode voltage) is defined as:
VOUT,dm = (V+OUT – V–OUT)
V+OUT and V–OUT refer to the voltages at the +OUT and –OUT
terminals with respect to a common reference.
Common-mode voltage refers to the average of two node volt-
ages. The output common-mode voltage is defined as:
VOUT,cm = (V+OUT + V–OUT)/2
Balance is a measure of how well differential signals are matched
in amplitude and exactly 180 degrees apart in phase. Balance is
most easily determined by placing a well-matched resistor di-
vider between the differential voltage nodes and comparing the
magnitude of the signal at the divider’s midpoint with the mag-
nitude of the differential signal. (See Figure 27.) By this definition,
output balance is the magnitude of the output common-mode
voltage divided by the magnitude of the output differential-
mode voltage:
Output Balance Error
V
OUT cm
OUT dm
=
,
THEORY OF OPERATION
The AD8138 differs from conventional op amps in that it has
two outputs whose voltages move in opposite directions. Like an
op amp, it relies on high open loop gain and negative feedback
to force these outputs to the desired voltages. The AD8138 be-
haves much like a standard voltage feedback op amp and makes
it easy to perform single-ended-to-differential conversion,
common-mode level-shifting, and amplification of differential
signals. Also like an op amp, the AD8138 has high input imped-
ance and low output impedance.
Previous differential drivers, both discrete and integrated de-
signs, have been based on using two independent amplifiers,
and two independent feedback loops, one to control each of the
outputs. When these circuits are driven from a single-ended
source, the resulting outputs are typically not well balanced.
Achieving a balanced output has typically required exceptional
matching of the amplifiers and feedback networks.
DC common-mode level-shifting has also been difficult with
previous differential drivers. Level-shifting has required the use
of a third amplifier and feedback loop to control the output
common-mode level. Sometimes the third amplifier has also
been used to attempt to correct an inherently unbalanced
circuit. Excellent performance over a wide frequency range has
proven difficult with this approach.
The AD8138 uses two feedback loops to separately control the
differential and common-mode output voltages. The differential
feedback, set with external resistors, controls only the differen-
tial output voltage. The common-mode feedback controls only
the common-mode output voltage. This architecture makes it
easy to arbitrarily set the output common-mode level. It is forced,
by internal common-mode feedback, to be equal to the voltage
applied to the VOCM input, without affecting the differential
output voltage.
The AD8138 architecture results in outputs that are very highly
balanced over a wide frequency range without requiring tightly
matched external components. The common-mode feedback
loop forces the signal component of the output common-mode
voltage to be zeroed. The result is nearly perfectly balanced
differential outputs, of identical amplitude and exactly 180
degrees apart in phase.
Analyzing an Application Circuit
The AD8138 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs labeled +IN and –IN in Figure
36. For most purposes, this voltage can be assumed to be zero.
Similarly, the difference between the actual output common-
mode voltage and the voltage applied to VOCM can also be as-
sumed to be zero. Starting from these two assumptions, any
application circuit can be analyzed.
Setting the Closed Loop Gain
Neglecting the capacitors CF, the differential mode gain of the
circuit in Figure 36 can be determined to be described by the
following equation:
V
R
OUT dm
IN dm
F
S
G
S
,
=
This assumes the input resistors, RG
S and feedback resistors,
RF
S on each side are equal.
Estimating the Output Noise Voltage
Similar to the case of a conventional op amp, the differential
output errors (noise and offset voltages) can be estimated by
multiplying the input referred terms, at +IN and –IN, by the
circuit noise gain. The noise gain is defined as:
G
R
N
F
G
=+
1
To compute the total output referred noise for the circuit of
Figure 36, consideration must also be given to the contribution
of the resistors RF and RG. Refer to Table I for estimated output
noise voltage densities at various closed-loop gains.
Table I
RG
RF
Bandwidth
Output Noise
Gain
( )( )
–3 dB
8138 Only
8138 + RG, RF
1
499
320 MHz
10 nV/
√Hz
11.5 nV/
√Hz
2
499
1.0 k
180 MHz
15 nV/
√Hz
16.6 nV/
√Hz
5
499
2.49 k 70 MHz
30 nV/
√Hz
31.6 nV/
√Hz
10
499
4.99 k 30 MHz
55 nV/
√Hz
56.6 nV/
√Hz
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