VOCM
參數(shù)資料
型號(hào): AD8138AR
廠商: Analog Devices Inc
文件頁(yè)數(shù): 24/25頁(yè)
文件大小: 0K
描述: IC AMP DIFF LDIST LP 95MA 8SOIC
設(shè)計(jì)資源: DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7352 (CN0040)
DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7356 (CN0041)
DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7357 (CN0061)
標(biāo)準(zhǔn)包裝: 98
類型: ADC 驅(qū)動(dòng)器
應(yīng)用: 數(shù)據(jù)采集
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 管件
AD8138
Rev. F | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Ratings
Supply Voltage
±5.5 V
VOCM
±VS
Internal Power Dissipation
550 mW
Operating Temperature Range
40°C to +85°C
Storage Temperature Range
65°C to +150°C
Lead Temperature (Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.
Table 6.
Package Type
θJA
Unit
8-Lead SOIC/4-Layer
121
°C/W
8-Lead MSOP/4-Layer
145
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8138 packages
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8138. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of the differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
internal common-mode feedback loop. The internal resistor tap
used in the common-mode feedback loop places a negligible
differential load on the output. RMS voltages and currents
should be considered when dealing with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces through holes, ground,
and power planes reduces the θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(121°C/W) and 8-lead MSOP (θJA = 145°C/W) packages on a
JEDEC standard 4-layer board. θJA values are approximations.
AMBIENT TEMPERATURE (°C)
MA
X
IM
U
M
PO
W
E
R
D
ISSI
PA
T
IO
N
(
W
)
1.75
1.50
1.00
1.25
0.50
0.25
0.75
0
SOIC
MSOP
01
07
3-
0
49
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80 90 100 110 120
Figure 3. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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