to bias VIN
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD8139ARD
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 15/25闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC AMP DIFF R-R LN LDIST 8SOIC
妯欐簴鍖呰锛� 98
鏀惧ぇ鍣ㄩ鍨嬶細 宸垎
闆昏矾鏁�(sh霉)锛� 1
杓稿嚭椤炲瀷锛� 宸垎锛屾豢鎿哄箙
杞�(zhu菐n)鎻涢€熺巼锛� 800 V/µs
-3db甯跺锛� 410MHz
闆绘祦 - 杓稿叆鍋忓锛� 2.25µA
闆诲 - 杓稿叆鍋忕Щ锛� 150µV
闆绘祦 - 闆绘簮锛� 24.5mA
闆绘祦 - 杓稿嚭 / 閫氶亾锛� 100mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 4.5 V ~ 12 V锛�±2.25 V ~ 6 V
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm Width锛夎8闇茬剨鐩�
渚涙噳鍟嗚ō鍌欏皝瑁濓細 8-SOIC-EP
鍖呰锛� 绠′欢
AD8139
Rev. B | Page 21 of 24
One way to avoid the input common-mode swing limitation is
to bias VIN and VREF at midsupply. In this case, VIN is 5 V p-p
swinging about a baseline at 2.5 V, and VREF is connected to a
low-Z 2.5 V source. VICM now has an amplitude of 2.5 V p-p and
is swinging about 2.5 V. Using the results in Equation 17, VACM
is calculated to be equal to VICM because VOCM = VICM. Therefore,
VACM swings from 1.25 V to 3.75 V, which is well within the
input common-mode voltage limits of the AD8139. Another
benefit seen in this example is that because VOCM = VACM = VICM
no wasted common-mode current flows. Figure 62 illustrates
how to provide the low-Z bias voltage. For situations that do not
require a precise reference, a simple voltage divider suffices to
develop the input voltage to the buffer.
VIN
0V TO 5V
AD8139
+
鈥�
8
2
1
6
3
4
5
VOCM
200
324
5V
200
324
0.1F
10F
+
AD8031
+
鈥�
0.1F
5V
ADR431
2.5V
REFERENCE
TO AD7674 REFBUFIN
046
79
-0
53
Figure 62. Low-Z 2.5 V Buffer
Another way to avoid the input common-mode swing limitation is
to use dual power supplies on the AD8139. In this case, the
biasing circuitry is not required.
Bandwidth vs. Closed-Loop Gain
The 3 dB bandwidth of the AD8139 decreases proportionally
to increasing closed-loop gain in the same way as a traditional
voltage feedback operational amplifier. For closed-loop gains
greater than 4, the bandwidth obtained for a specific gain can be
estimated as
)
MHz
300
(
,
dB
3
,
+
=
F
G
dm
OUT
R
V
f
(20)
or equivalently, 尾(300 MHz).
This estimate assumes a minimum 90掳 phase margin for the
amplifier loop, which is a condition approached for gains greater
than 4. Lower gains show more bandwidth than predicted by
the equation due to the peaking produced by the lower
phase margin.
Estimating DC Errors
Primary differential output offset errors in the AD8139 are due
to three major components: the input offset voltage, the offset
between the VAN and VAP input currents interacting with the
feedback network resistances, and the offset produced by the dc
voltage difference between the input and output common-mode
voltages in conjunction with matching errors in the feedback
network.
The first output error component is calculated as
+
=
G
F
IO
R
V
e1
Vo _
, or equivalently as VIO/尾
(21)
where VIO is the input offset voltage. The input offset voltage of the
AD8139 is laser trimmed and guaranteed to be less than 500 渭V.
The second error is calculated as
()
F
IO
G
F
G
F
IO
R
I
R
I
e2
Vo
=
+
+
=
_
(22)
where IIO is defined as the offset between the two input bias
currents.
The third error voltage is calculated as
Vo_e3 = 螖enr 脳 (VICM VOCM)
(23)
where 螖enr is the fractional mismatch between the two
feedback resistors.
The total differential offset error is the sum of these three error
sources.
Other Impact of Mismatches in the Feedback Networks
The internal common-mode feedback network still forces the
output voltages to remain balanced, even when the RF/RG feedback
networks are mismatched. However, the mismatch will cause a
gain error proportional to the feedback network mismatch.
Ratio-matching errors in the external resistors degrade the
ability to reject common-mode signals at the VAN and VIN input
terminals, much the same as with a four-resistor difference
amplifier made from a conventional op amp. Ratio-matching
errors also produce a differential output component that is
equal to the VOCM input voltage times the difference between the
feedback factors (尾s). In most applications using 1% resistors,
this component amounts to a differential dc offset at the output
that is small enough to be ignored.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
PFC-W1206LF-03-4991-B-1059 RES PREC 4.99KOHM 333MW .1% 1206
LT6604CUFF-5#TRPBF IC AMP DIFF LN DUAL 34-QFN
LT6604CUFF-2.5#TRPBF IC AMP DIFF LN DUAL 34-QFN
52601-S10-8 LP.100"SHRD HDR .100" VERT 15GLD
3793-1303 CONN HEADER 10POS R/A LONG LATCH
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鍙冩暩(sh霉)鎻忚堪
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