參數(shù)資料
型號: AD8141ACPZ-R7
廠商: Analog Devices Inc
文件頁數(shù): 13/24頁
文件大?。?/td> 0K
描述: IC AMP VIDEO TRIPLE DR 24-LFCSP
標準包裝: 1
應用: 驅(qū)動器
輸出類型: 差分
電路數(shù): 3
-3db帶寬: 275MHz
轉(zhuǎn)換速率: 1150 V/µs
電流 - 電源: 44mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 5.5 V,±2.25 V ~ 2.75 V
安裝類型: 表面貼裝
封裝/外殼: 24-WFQFN 裸露焊盤,CSP
供應商設(shè)備封裝: 24-LFCSP-WQ(4x4)
包裝: 標準包裝
其它名稱: AD8141ACPZ-R7DKR
AD8141/AD8142
Data Sheet
Rev. A | Page 20 of 24
AD8142 SIGNAL LEVELS ON VARIOUS SUPPLIES
Figure 44 and Figure 45 illustrate the key video signal levels
seen in typical applications operating on a single +5 V supply
and ±2.5 V supplies; common-mode sync pulses are omitted
from the circuit drawing for clarity but are shown in a separate
waveform drawing of the signals directly at the AD8142 outputs,
shown just below the associated circuit drawing. The sync pulses
are common-mode, that is, they move in the same direction on
each output polarity. In Figure 44 and Figure 45, this means that
the HSYNC pulses are either both green or both blue for the red
and black video signals.
DISABLE FEATURE
When asserted, the disable feature minimizes quiescent current
consumption and provides a high-Z output. It offers a convenient
means to connect two driver outputs together in parallel to form a
tristate multiplexed application. The disable feature can also be
used to minimize quiescent current drawn when a particular
device is not being used.
The disable pin is a binary input that controls the state of the
AD8141/AD8142 outputs. Its binary input levels are compatible
with most TTL and CMOS families (see Table 1 for the logic
levels). The AD8141/AD8142output is disabled when the disable
input is driven to its high state, and the AD8141/AD8142
operates in its normal fashion when the disable input is driven to
its low state.
An unavoidable common-mode glitch occurs at the outputs
when switching between disabled and enabled states and vice
versa. The glitch lasts for a few tens of nanoseconds and is
on the order of 2 V or 3 V. If the disable feature is used, it is
recommended that common-mode protection be used on the
receiver (see the AD8143 data sheet for a detailed description of
common-mode protection)
09
46
1-
0
42
AD8142
+
49.9
1k
38.3
80.6
0.76V
0.52V
1k
2k
+5V
2k
100
UTP
49.9
0.7V
1.5V
2.2V
1.5V
0.8V
0.7V
0V
75
VIDEO
SOURCE
1.4V
1.5V
0.8V
2.2V
0.5V
AD8142 KEY SIGNAL LEVELS ON SINGLE +5V SUPPLY
AD8142 OUTPUT SIGNAL LEVELS INCLUDING COMMON-MODE HSYNC PULSES
Figure 44. AD8142 Key Signal Levels on Single 5 V Supply; Upper Drawing Shows Schematic, and Lower Drawing Shows Output Signals with HSYNC Pulses
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