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| 型號(hào)： | AD8145YCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC RECEIVER TRIPLE DIFF 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類(lèi)型： | 接收器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 0/3 |
| 規(guī)程： | 以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 24 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
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AD8145
Rev. A | Page 18 of 24
Figure 41 shows a specific example of external common-mode
clamping.
GAIN
REF
R
0.01F
+5V
–5V
C
OUT
VOUT
V+
V–
3
2
1
3
2
1
VIN
+
–
RT
RS
HBAT-540C
06
30
7-
04
2
Figure 41. External Common-Mode Clamping
The series resistances, RS, limit the current in each leg, and the
Schottky diodes limit the voltages on each input to approximately
0.3 V to 0.4 V over the positive power supply, V+, and to 0.3 V
to 0.4 V below the negative power supply, V. The required
signal bandwidth, the line impedance, and the effective
differential capacitance due to the AD8145 inputs and the
diodes determine the maximum RS value.
As with the differential clamp, the series resistors should be
highly matched in value to preserve high frequency CMRR.
PCB LAYOUT CONSIDERATIONS
The two most important issues with regard to PCB layout are
minimizing parasitic signal trace reactances in the feedback
network and providing sufficient thermal relief.
Excessive parasitic reactances in the feedback network cause
excessive peaking in the frequency response of the amplifier
and excessive overshoot in its step response due to a reduction
in phase margin. Oscillation occurs when these parasitic
reactances are increased to a critical point where the phase margin
is reduced to zero. Minimizing these reactances is important to
obtain optimal performance from the AD8145. General high
speed layout practices should be adhered to when applying the
AD8145. Controlled impedance transmission lines are required
for incoming and outgoing signals, referenced to a ground plane.
Typically, the input signals are received over 100 Ω differential
transmission lines. A 100 Ω differential transmission line is readily
realized on the PCB using two well-matched, closely-spaced,
50 Ω single-ended traces that are coupled through the ground
plane. The traces that carry the single-ended output signals are
most often 75 Ω for video signals. Output signal connections
should include series termination resistors that are matched to
the impedance of the line they are driving. When driving high
impedance loads over very short traces, impedance matching is
not required. In these cases, small series resistors should be used to
buffer the capacitance presented by the load.
Broadband power supply decoupling networks should be placed
as close as possible to the supply pins. Small surface-mount ceramic
capacitors are recommended for these networks, and tantalum
capacitors are recommended for bulk supply decoupling.
Minimizing Parasitic Feedback Reactances
Parasitic trace capacitance and inductance are both reduced in
the unity-gain configuration when the feedback trace that connects
the OUT_x pin to the GAIN_x pin is reduced in length. Removing
the copper from the planes below the trace reduces trace capacitance,
but increases trace inductance, because the loop area formed by
the trace and ground plane is increased. A reasonable compromise
that works well is to void all copper directly under the feedback
trace and component pads with margins on each side approximately
equal to one trace width. Combining this technique with minimizing
trace length is effective in keeping parasitic trace reactance in
the unity-gain feedback loop to a minimum.
Maximizing Heat Removal
A square array of thermal vias works well to connect the exposed
paddle to internal ground planes. The vias should be placed
inside the PCB pad that is soldered to the exposed paddle and
should connect to all ground planes.
The AD8145 includes ground connections on its corner pins.
These pins can be used to provide additional heat removal from
the AD8145 by connecting them between the PCB pad that is
soldered to the exposed paddle and a ground plane on the
component side of the board. This layout technique lowers the
overall package thermal resistance. Use of this technique is not
required, but it does result in a lower junction temperature. Designs
must often conform to Design for Manufacturing (DFM) rules
that stipulate how to lay out PCBs in such a way as to facilitate
the manufacturing process. Some of these rules require thermal
relief on pads that connect to planes, and the rules may limit the
extent to which this technique can be used.
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