參數(shù)資料
型號: AD8148ACPZ-R7
廠商: Analog Devices Inc
文件頁數(shù): 11/24頁
文件大?。?/td> 0K
描述: IC DRIVER TRIPLE DIFF 24-LFCSP
標(biāo)準(zhǔn)包裝: 1,500
應(yīng)用: 差分
輸出類型: 差分
電路數(shù): 3
-3db帶寬: 900MHz
轉(zhuǎn)換速率: 3000 V/µs
電流 - 電源: 62.5mA
電流 - 輸出 / 通道: 87mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 11 V,±2.25 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 24-LFCSP-VQ(4x4)
包裝: 帶卷 (TR)
Data Sheet
AD8146/AD8147/AD8148
Rev. B | Page 19 of 24
AD8146
CROSSPOINT SWITCH
54.9
1k
500
INPUT I, NEGATIVE PHASE
INPUT I, POSITIVE PHASE
INPUT J, NEGATIVE PHASE
INPUT J, POSITIVE PHASE
INPUT K, NEGATIVE PHASE
INPUT K, POSITIVE PHASE
10
VOCM
RED
CHANNEL
100
UTP
54.9
1k
500
10
VOCM
GREEN
CHANNEL
100
UTP
54.9
1k
500
10
VOCM
BLUE
CHANNEL
100
UTP
VS+ = +2.5V
VPOS = +2.5V
VNEG = –2.5V
VS– = –2.5V
09327-
035
Figure 35. Using the AD8146 as a Differential Receiver
Terminations are not required between the AD8146 and the
switch if the interconnection lengths are kept short (less than
two inches). The 10 series resistors buffer the input
capacitance of the switch (typically 2 pF) and produce a low-
pass rolloff that is down by only 0.025 dB at 600 MHz.
OUTPUT PULL-DOWN (OPD)
The output pull-down feature, when used in conjunction with
series Schottky diodes, offers a convenient means to multiplex a
number of driver outputs together to form a video network. The
OPD pin is a binary input that controls the state of the outputs.
Its binary input level is referenced to GND (see the Specifications
section for the logic levels). When the OPD input is driven to its
low state, the output is enabled and operates in normal fashion.
In this state, the VOCM input can be used to provide a positive
bias on the series diodes, allowing the drivers to transmit
signals over the network. When the OPD input is driven to its
high state, the outputs of the drivers are forced to a low voltage,
irrespective of the level on the VOCM input, reverse-biasing the
series diodes and thus presenting high impedance to the
network. This feature allows a three-state output to be realized
that maintains its high impedance state even when the drivers
are not powered.
It is recommended that the output pull-down feature only be
used in conjunction with series diodes in such a way as to
ensure that the diodes are reverse-biased when the output pull-
down feature is asserted, because some loading conditions can
prevent the output voltage from being pulled all the way down.
LAYOUT AND POWER SUPPLY DECOUPLING
CONSIDERATIONS
Standard high speed PCB layout practices should be adhered
to when designing with the drivers. A solid ground plane is
required and good wideband power supply decoupling
networks should be placed as close as possible to the supply
pins. Small surface-mount ceramic capacitors are recommended
for these networks, and tantalum capacitors are recommended
for bulk supply decoupling.
Source termination resistors on the differential outputs must be
placed as close as possible to the output pins to minimize load
capacitance due to the PCB traces.
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the output impedance
of any amplifier to produce an undesirable phase shift, which
reduces phase margin and results in high frequency ringing in
the pulse response. The best way to minimize this effect is to
place a small resistor in series with each of the outputs of the
amplifier to buffer the load capacitance. Most applications
include 49.9 source termination resistors, which effectively
buffer any stray load capacitance.
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